From f04ecca4077b5f8723b2a8e0a125bfeacc44214a Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 13:57:55 +0100 Subject: single frequency implementation --- basys3/basys3.srcs/apu_LUT_reader.vhd | 56 ++++++++++++++++++++++++++++++++ basys3/basys3.srcs/apu_tb_LUT_reader.vhd | 48 +++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 basys3/basys3.srcs/apu_LUT_reader.vhd create mode 100644 basys3/basys3.srcs/apu_tb_LUT_reader.vhd diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd new file mode 100644 index 0000000..2dd3b06 --- /dev/null +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -0,0 +1,56 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity apu_LUT_reader is + port ( + clk : in std_logic; + rst : in std_logic; + freq : in std_logic_vector(11 downto 0); + wave : in std_logic_vector(1 downto 0); + value : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture Behavioral of apu_LUT_reader is + + signal idx : std_logic_vector(7 downto 0) := (others => '0'); + signal buf : unsigned := (others => '0'); + +begin + + process (clk) + begin + if rst = '1' then + idx <= x"00"; + buf <= x"00"; + elsif rising_edge(clk) then + --main code here + + if wave = "00" then --Sawtooth + value <= idx; + elsif wave = "01" then --Square + if (signed(idx) < 128) then + value <= x"00"; + else + value <= x"FF"; + end if; + elsif wave = "10" then --Triangle + value <= std_logic_vector( abs(signed(idx)-127)*2 ); + else--wave = "11" then --Noise + --implement noise function here: + value <= x"80"; --remove this + end if; + + + + if unsigned(idx) < 255 then --moves to next index value + idx <= std_logic_vector( unsigned(idx) + '1'); + else + idx <= x"00"; + end if; + + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd new file mode 100644 index 0000000..d4ed935 --- /dev/null +++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity apu_tb_LUT_reader is +end entity; + +architecture Behavioral of apu_tb_LUT_reader is + component apu_LUT_reader is + port ( + clk : in std_logic; + rst : in std_logic; + freq : in std_logic_vector(11 downto 0); + wave : in std_logic_vector(1 downto 0); + value : out std_logic_vector(7 downto 0) + ); + end component; + + signal OK : boolean := false; + + signal clk : std_logic := '0'; + signal rst : std_logic := '0'; + signal freq : std_logic_vector(11 downto 0) := (others => '0'); + signal wave : std_logic_vector(1 downto 0) := (others => '0'); + +begin + + TB: process + begin + wave <= "00"; + for I in 0 to 255 loop + clk <= '1'; + + -- freq <= '1'; + + + wait for 1 ps; + clk <= '0'; + wait for 1 ps; + + + end loop; + end process; + +end architecture; \ No newline at end of file -- cgit v1.2.3 From 3739edf5d5adc7a79aa9fd050d45493d697eaa92 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 14:02:12 +0100 Subject: apu_LUT_reader made with variable frequency --- basys3/basys3.srcs/apu_LUT_reader.vhd | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index 2dd3b06..a37cd30 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -44,10 +44,15 @@ begin - if unsigned(idx) < 255 then --moves to next index value - idx <= std_logic_vector( unsigned(idx) + '1'); + if buf < unsigned(freq) then -- change frequency + buf <= buf + 1; else - idx <= x"00"; + buf <= x"00"; + if unsigned(idx) < 255 then --moves to next index value + idx <= std_logic_vector( unsigned(idx) + '1'); + else + idx <= x"00"; + end if; end if; end if; -- cgit v1.2.3 From e93383878d3784b390f0ab3a9514de6ce3dedb2a Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 15:55:37 +0100 Subject: polish on APU_N2F --- basys3/basys3.srcs/apu_note_to_frequency.vhd | 39 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd index 878da30..b8f561b 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd @@ -6,35 +6,36 @@ entity apu_note_to_frequency is port ( -- clk : in std_logic; -- rst : in std_logic; - data : in std_logic_vector(7 downto 0); - freq : out std_logic_vector(11 downto 0) --frequency + data : in std_logic_vector(6 downto 0); + freq : out std_logic_vector(11 downto 0) -- frequency ); end entity; architecture Behavioral of apu_note_to_frequency is signal buffSmall : std_logic_vector(7 downto 0) := (others => '0'); -signal buff : std_logic_vector(15 downto 0) := (others => '0'); +signal buff : std_logic_vector(11 downto 0) := (others => '0'); signal shift : integer; begin shift <= to_integer(unsigned( data(2 downto 0) )); - buffSmall <= - x"F0" when data(7 downto 3) = (x"C" & '0') else -- C 496 - x"D0" when data(7 downto 3) = (x"C" & '1') else -- C# 464 - x"B0" when data(7 downto 3) = (x"D" & '0') else -- D 432 - x"A0" when data(7 downto 3) = (x"D" & '1') else -- D# 416 - x"80" when data(7 downto 3) = (x"E" & '0') else -- E 384 - x"70" when data(7 downto 3) = (x"F" & '0') else -- F 368 - x"58" when data(7 downto 3) = (x"F" & '1') else -- F# 344 - x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320 - x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304 - x"20" when data(7 downto 3) = (x"A" & '0') else -- A 288 - x"10" when data(7 downto 3) = (x"A" & '1') else -- A# 272 - x"00" when data(7 downto 3) = (x"B" & '0') else -- B 256 - x"01"; + buff <= + x"1F0" when data(6 downto 3) = (x"1") else -- C 496 + x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464 + x"1B0" when data(6 downto 3) = (x"3") else -- D 432 + x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416 + x"180" when data(6 downto 3) = (x"5") else -- E 384 + x"170" when data(6 downto 3) = (x"6") else -- F 368 + x"158" when data(6 downto 3) = (x"7") else -- F#/Gb 344 + x"140" when data(6 downto 3) = (x"8") else -- G 320 + x"130" when data(6 downto 3) = (x"9") else -- G#/Ab 304 + x"120" when data(6 downto 3) = (x"A") else -- A 288 + x"110" when data(6 downto 3) = (x"B") else -- A#/Bb 272 + x"100" when data(6 downto 3) = (x"C") else -- B 256 + x"000"; - buff <= x"1" & buffSmall; - freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2) + -- buff <= x"1" & buffSmall; + freq <= std_logic_vector( shift_right(unsigned(buff), shift) ); + -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');) end architecture; \ No newline at end of file -- cgit v1.2.3 From f28e1ceec5b9a6ee3f156c3f032eb7a78a08f401 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 16:20:20 +0100 Subject: shifted triangle wave 180* --- basys3/basys3.srcs/apu_LUT_reader.vhd | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index a37cd30..e56f855 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -14,7 +14,10 @@ end entity; architecture Behavioral of apu_LUT_reader is - signal idx : std_logic_vector(7 downto 0) := (others => '0'); + constant AMPLITUDE : natural := 0; + constant SAMPLE_SIZE : natural := 256; + + signal idx : unsigned := (others => '0'); signal buf : unsigned := (others => '0'); begin @@ -25,21 +28,25 @@ begin idx <= x"00"; buf <= x"00"; elsif rising_edge(clk) then - --main code here + -- main code here - if wave = "00" then --Sawtooth - value <= idx; - elsif wave = "01" then --Square - if (signed(idx) < 128) then + if wave = "00" then -- Sawtooth + value <= std_logic_vector( idx ); + elsif wave = "01" then -- Square + if idx < (SAMPLE_SIZE/2) then value <= x"00"; else value <= x"FF"; end if; - elsif wave = "10" then --Triangle - value <= std_logic_vector( abs(signed(idx)-127)*2 ); - else--wave = "11" then --Noise - --implement noise function here: - value <= x"80"; --remove this + elsif wave = "10" then -- Triangle + if idx < (SAMPLE_SIZE/2) then + value <= std_logic_vector( idx*2 ); + else + value <= std_logic_vector( (SAMPLE_SIZE-idx)*2 ); + end if; + else-- wave = "11" then -- Noise + -- TODO: implement noise function here: + value <= x"80"; -- remove this end if; @@ -48,8 +55,8 @@ begin buf <= buf + 1; else buf <= x"00"; - if unsigned(idx) < 255 then --moves to next index value - idx <= std_logic_vector( unsigned(idx) + '1'); + if idx < (SAMPLE_SIZE-1) then -- moves to next index value + idx <= idx + 1; else idx <= x"00"; end if; @@ -58,4 +65,4 @@ begin end if; end process; -end architecture; \ No newline at end of file +end architecture; -- cgit v1.2.3 From c3b877f0503ce995bd79ed3f4eb74d7370839582 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 16:30:24 +0100 Subject: small formatting fix --- basys3/basys3.srcs/apu_LUT_reader.vhd | 5 +++-- basys3/basys3.srcs/apu_tb_LUT_reader.vhd | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index e56f855..6039798 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity apu_LUT_reader is port ( - clk : in std_logic; + clk : in std_logic; rst : in std_logic; freq : in std_logic_vector(11 downto 0); wave : in std_logic_vector(1 downto 0); @@ -27,6 +27,7 @@ begin if rst = '1' then idx <= x"00"; buf <= x"00"; + value <= x"00"; elsif rising_edge(clk) then -- main code here @@ -34,7 +35,7 @@ begin value <= std_logic_vector( idx ); elsif wave = "01" then -- Square if idx < (SAMPLE_SIZE/2) then - value <= x"00"; + value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave) else value <= x"FF"; end if; diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd index d4ed935..5a38d39 100644 --- a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd @@ -45,4 +45,4 @@ begin end loop; end process; -end architecture; \ No newline at end of file +end architecture; -- cgit v1.2.3