From 49a935b6276e59d48665b6ab6e72ff475173bb67 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Thu, 23 Mar 2023 18:25:16 +0100 Subject: WIP testing ppu (fixed BAM 2nat buffer overflow) --- basys3/basys3.srcs/.gitignore | 1 + basys3/basys3.srcs/io.xdc | 2 - basys3/basys3.srcs/makefile | 5 + basys3/basys3.srcs/ppu_tb.vhd.m4 | 54 ++ basys3/basys3.xpr | 49 +- src/ppu/internals.c | 2 +- test/ppu-stm-integration-demo/.gitignore | 1 + test/ppu-stm-integration-demo/data2vhdltb.awk | 16 + test/ppu-stm-integration-demo/makefile | 12 +- test/ppu-stm-integration-demo/test-image.txt | 1200 ------------------------- 10 files changed, 115 insertions(+), 1227 deletions(-) create mode 100644 basys3/basys3.srcs/.gitignore create mode 100644 basys3/basys3.srcs/makefile create mode 100644 basys3/basys3.srcs/ppu_tb.vhd.m4 create mode 100755 test/ppu-stm-integration-demo/data2vhdltb.awk diff --git a/basys3/basys3.srcs/.gitignore b/basys3/basys3.srcs/.gitignore new file mode 100644 index 0000000..dd85c9b --- /dev/null +++ b/basys3/basys3.srcs/.gitignore @@ -0,0 +1 @@ +ppu_tb.vhd diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc index 85d4fc2..8243f1e 100644 --- a/basys3/basys3.srcs/io.xdc +++ b/basys3/basys3.srcs/io.xdc @@ -1,9 +1,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI] -set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS] set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK] set_property PACKAGE_PIN J2 [get_ports SPI_CLK] -set_property PACKAGE_PIN C15 [get_ports SPI_CS] set_property PACKAGE_PIN L2 [get_ports SPI_MOSI] set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK] diff --git a/basys3/basys3.srcs/makefile b/basys3/basys3.srcs/makefile new file mode 100644 index 0000000..61fab40 --- /dev/null +++ b/basys3/basys3.srcs/makefile @@ -0,0 +1,5 @@ +ppu_tb.vhd: ppu_tb.vhd.m4 ../../test/ppu-stm-integration-demo/test-image.tb.vhd + +%.vhd: %.vhd.m4 + m4 -I../../test/ppu-stm-integration-demo/ $< > $@ + diff --git a/basys3/basys3.srcs/ppu_tb.vhd.m4 b/basys3/basys3.srcs/ppu_tb.vhd.m4 new file mode 100644 index 0000000..0797c9f --- /dev/null +++ b/basys3/basys3.srcs/ppu_tb.vhd.m4 @@ -0,0 +1,54 @@ +library ieee; +library unisim; +use ieee.std_logic_1164.all; +use work.ppu_consts.all; +use unisim.vcomponents.all; + +entity ppu_tb is +end ppu_tb; + +architecture behavioral of ppu_tb is + component ppu port( + CLK100 : in std_logic; -- system clock + RESET : in std_logic; -- global (async) system reset + WEN : in std_logic; -- PPU VRAM write enable + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR + DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + VSYNC, HSYNC : out std_logic; -- VGA sync out + VBLANK : out std_logic); -- vblank for synchronization + end component; + signal CLK100, RESET, WEN : std_logic := '0'; + signal ADDR : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); + signal DATA : std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); +begin + uut : ppu port map ( + CLK100 => CLK100, + RESET => RESET, + WEN => WEN, + ADDR => ADDR, + DATA => DATA, + R => open, + G => open, + B => open, + VSYNC => open, + HSYNC => open, + VBLANK => open); + + process + begin + for i in 0 to 3200000 loop + wait for 5 ns; + CLK100 <= '1'; + wait for 5 ns; + CLK100 <= '0'; + end loop; + wait; -- stop for simulator + end process; + + process + begin + -- undivert(`test-image.tb.vhd') -- m4 macro expansion (see makefile) + wait; -- stop after one loop (process loops in simulator) + end process; +end Behavioral; diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 82d7be5..acb43b0 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -44,6 +44,7 @@