From 6cd57aed4fa4d8617c602a0efa4856ea58aa2e0e Mon Sep 17 00:00:00 2001 From: lonkaars Date: Fri, 10 Mar 2023 14:54:47 +0100 Subject: move pinout.md to schematic --- docs/hardware/.gitignore | 1 + docs/hardware/hardware.kicad_pcb | 2 + docs/hardware/hardware.kicad_prl | 77 ++ docs/hardware/hardware.kicad_pro | 332 ++++++ docs/hardware/hardware.kicad_sch | 2050 ++++++++++++++++++++++++++++++++++++++ pinout.md | 33 - 6 files changed, 2462 insertions(+), 33 deletions(-) create mode 100644 docs/hardware/.gitignore create mode 100644 docs/hardware/hardware.kicad_pcb create mode 100644 docs/hardware/hardware.kicad_prl create mode 100644 docs/hardware/hardware.kicad_pro create mode 100644 docs/hardware/hardware.kicad_sch delete mode 100644 pinout.md diff --git a/docs/hardware/.gitignore b/docs/hardware/.gitignore new file mode 100644 index 0000000..8b1ed53 --- /dev/null +++ b/docs/hardware/.gitignore @@ -0,0 +1 @@ +hardware-backups/ diff --git a/docs/hardware/hardware.kicad_pcb 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eb556876-5e74-477c-a234-961fdee63b80)) + (pin "T19" (uuid 78e4f078-c50d-4247-b3c6-395f96753c50)) + (pin "U6" (uuid a4ca2684-c081-4ec3-89d2-94593ee94c99)) + (pin "U9" (uuid a7b15dc9-ee2d-4926-8d91-fc82a85ae869)) + (pin "V18" (uuid af9811a7-ba98-4884-90b2-31fea8c76766)) + (pin "W1" (uuid e358d629-fe18-4c15-9260-93f122fe82e5)) + (pin "W12" (uuid 6523c6ec-7bab-477c-86f6-9220d4242ac0)) + (instances + (project "hardware" + (path "/9c6bd711-93fb-4327-8ec4-bcfe43c3c3c8" + (reference "U2") (unit 1) + ) + ) + ) + ) + + (sheet_instances + (path "/" (page "1")) + ) +) diff --git a/pinout.md b/pinout.md deleted file mode 100644 index f4569d2..0000000 --- a/pinout.md +++ /dev/null @@ -1,33 +0,0 @@ -Pin layout - -| pin STM | function | -|---------|----------| -| PA5 / D13 | SPI clock | -| PA7 / D11 | SPI MOSI | -| PA9 / D8 | SPI cs | -| PB4 / D5 | button 1 | -| PB5 / D4 | button 2 | -| PB6 / D10 | button 3 | -| PB8 / D15 | button 4 | - -| pin FPGA | function | -|---------|----------| -| JB 7 | SPI clock | -| JB 8 | SPI data | -| JB 9 | SPI cs | - - - -constraints: - -set_property PACKAGE_PIN A15 [get_ports clkSPI] - -set_property PACKAGE_PIN C15 [get_ports csSPI] - -set_property PACKAGE_PIN A17 [get_ports dataSPI] - -set_property IOSTANDARD LVCMOS33 [get_ports dataSPI] - -set_property IOSTANDARD LVCMOS33 [get_ports csSPI] - -set_property IOSTANDARD LVCMOS33 [get_ports clkSPI] . -- cgit v1.2.3 From 80e2732c8f208f3f225a2a5c0e540bc50fceab5d Mon Sep 17 00:00:00 2001 From: lonkaars Date: Fri, 10 Mar 2023 16:09:10 +0100 Subject: top.vhdl --- basys3/basys3.srcs/io.xdc | 12 ++-- basys3/basys3.srcs/ppu.vhd | 10 ++- basys3/basys3.srcs/spi.vhd | 71 ++++++++++++++++++++ basys3/basys3.srcs/top.vhd | 164 +++++++++++++++++---------------------------- basys3/basys3.xpr | 22 +++++- 5 files changed, 163 insertions(+), 116 deletions(-) create mode 100644 basys3/basys3.srcs/spi.vhd diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc index f254cdd..fa1dbd0 100644 --- a/basys3/basys3.srcs/io.xdc +++ b/basys3/basys3.srcs/io.xdc @@ -1,6 +1,6 @@ -set_property PACKAGE_PIN A15 [get_ports clkSPI] -set_property PACKAGE_PIN C15 [get_ports csSPI] -set_property PACKAGE_PIN A17 [get_ports dataSPI] -set_property IOSTANDARD LVCMOS33 [get_ports dataSPI] -set_property IOSTANDARD LVCMOS33 [get_ports csSPI] -set_property IOSTANDARD LVCMOS33 [get_ports clkSPI] \ No newline at end of file +set_property PACKAGE_PIN A15 [get_ports SPI_CLK] +set_property PACKAGE_PIN C15 [get_ports SPI_CS] +set_property PACKAGE_PIN A17 [get_ports SPI_MOSI] +set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI] +set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS] +set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK] diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd index 9cf1bc0..d6407df 100644 --- a/basys3/basys3.srcs/ppu.vhd +++ b/basys3/basys3.srcs/ppu.vhd @@ -14,7 +14,7 @@ entity ppu is port( DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); NVSYNC, NHSYNC : out std_logic; -- native VGA out - TVSYNC, TVBLANK, THSYNC, THBLANK : out std_logic); -- tiny VGA out + TVBLANK, THBLANK : out std_logic); -- tiny VGA out end ppu; architecture Behavioral of ppu is @@ -189,7 +189,7 @@ architecture Behavioral of ppu is signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); signal FG_FETCH : std_logic; - signal TINY_VBLANK, TINY_VSYNC, TINY_HBLANK, TINY_HSYNC, + signal TINY_VBLANK, TINY_HBLANK, NATIVE_VSYNC, NATIVE_HSYNC : std_logic; begin SYSCLK <= CLK100; @@ -205,9 +205,7 @@ begin PAL_AI <= (others => '0'); TVBLANK <= TINY_VBLANK; - TVSYNC <= TINY_VSYNC; THBLANK <= TINY_HBLANK; - THSYNC <= TINY_HSYNC; NVSYNC <= NATIVE_VSYNC; NHSYNC <= NATIVE_HSYNC; @@ -334,9 +332,9 @@ begin RESET => SYSRST, X => X, Y => Y, - VSYNC => TINY_VSYNC, + VSYNC => open, VBLANK => TINY_VBLANK, - HSYNC => TINY_HSYNC, + HSYNC => open, HBLANK => TINY_HBLANK); native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler) diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd new file mode 100644 index 0000000..cdf7d4a --- /dev/null +++ b/basys3/basys3.srcs/spi.vhd @@ -0,0 +1,71 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use work.ppu_consts.all; + +entity spi is port ( + SYSCLK : in std_logic; -- clock basys3 100MHz + SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_MOSI : in std_logic; -- incoming data of SPI + SPI_CS : in std_logic; -- incoming select of SPI + DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read +end spi; + +architecture Behavioral of spi is + signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI + signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI + signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0'; -- signal for metastability synchronizer of slave select SPI + + signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); -- signal to store incomming data of dataSPI (2x 8bit) + signal counter : integer := 23; -- counter for data position + signal enable : std_logic := '0'; -- enable signal if slave is selected +begin + + process (SYSCLK) + begin + if rising_edge(SYSCLK) then + -- flip flop for clk SPI to synchronise a + PulseFF0 <= SPI_CLK; + PulseFF1 <= PulseFF0; + PulseFF2 <= PulseFF1; + PulseFF3 <= PulseFF2; + -- flip flop for data SPI to synchronise + dataFF0 <= SPI_MOSI; + dataFF1 <= dataFF0; + dataFF2 <= dataFF1; + dataFF3 <= dataFF2; + -- flip flop for slave select SPI to synchronise + ssFF0 <= SPI_CS; + ssFF1 <= ssFF0; + ssFF2 <= ssFF1; + ssFF3 <= ssFF2; + -- check if slave select signal has falling edge (slave is selected by master) + if(ssFF3 = '1' and ssFF2 = '0') then + -- reset counter if true + counter <= 23; + -- disable data read if rising edge (slave is not selected) + elsif (ssFF3 = '0' and ssFF2 = '1') then + enable <= '0'; + end if; + -- check if synchronised slave select signal is falling edge or data read is enabled + if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then + enable <= '1'; -- enable data read + if (PulseFF3 = '0' and PulseFF2 = '1') then -- check for rising edge of clk SPI + if counter > -1 then + counter <= counter - 1; + -- data transfer into vector + SPI_REG(counter) <= dataFF3; + end if; + end if; + -- check if counter is done + if counter = -1 then + counter <= 23; -- reset counter + DATA <= SPI_REG; + end if; + elsif (enable = '0') then + -- DATA <= SPI_REG; + end if; + end if; + end process; +end Behavioral; diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index 7cf3e63..558489b 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -1,105 +1,63 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.02.2023 21:09:16 --- Design Name: --- Module Name: top - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values -use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity spiSlave is - Port ( clkBoard : in std_logic; -- clock basys3 100MHz - clkSPI : in std_logic; -- incoming clock of SPI - dataSPI : in std_logic; -- incoming data of SPI - csSPI : in std_logic; -- incoming select of SPI - dataRead : out std_logic_vector(23 downto 0) := (others => '0') -- data read - - ); -end spiSlave; - -architecture Behavioral of spiSlave is - signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI - signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI - signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0'; -- signal for metastability synchronizer of slave select SPI - - signal data : std_logic_vector(23 downto 0) := (others => '0'); -- signal to store incomming data of dataSPI (2x 8bit) - signal counter : integer := 23; --counter for data position - signal enable : std_logic := '0'; -- enable signal if slave is selected +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.ppu_consts.all; + +entity top is port ( + SYSCLK : in std_logic; -- clock basys3 100MHz + RESET : in std_logic; -- global (async) system reset + SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_MOSI : in std_logic; -- incoming data of SPI + SPI_CS : in std_logic; -- incoming select of SPI + WEN : in std_logic; -- PPU VRAM write enable + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + NVSYNC, NHSYNC : out std_logic; -- native VGA out + TVBLANK, THBLANK : out std_logic); -- tiny VGA out +end top; + +architecture Behavioral of top is + component ppu port( + CLK100 : in std_logic; -- system clock + RESET : in std_logic; -- global (async) system reset + EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) + WEN : in std_logic; -- PPU VRAM write enable + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR + DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + NVSYNC, NHSYNC : out std_logic; -- native VGA out + TVBLANK, THBLANK : out std_logic); -- tiny VGA out + end component; + component spi port ( + SYSCLK : in std_logic; -- clock basys3 100MHz + SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_MOSI : in std_logic; -- incoming data of SPI + SPI_CS : in std_logic; -- incoming select of SPI + DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read + end component; + + signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + alias SPI_DATA_ADDR is SPI_DATA(31 downto 16); + alias SPI_DATA_DATA is SPI_DATA(15 downto 0); begin - - process (clkBoard) - begin - - if rising_edge(clkBoard) then - -- flip flop for clk SPI to synchronise a - PulseFF0 <= clkSPI; - PulseFF1 <= PulseFF0; - PulseFF2 <= PulseFF1; - PulseFF3 <= PulseFF2; - -- flip flop for data SPI to synchronise - dataFF0 <= dataSPI; - dataFF1 <= dataFF0; - dataFF2 <= dataFF1; - dataFF3 <= dataFF2; - -- flip flop for slave select SPI to synchronise - ssFF0 <= csSPI; - ssFF1 <= ssFF0; - ssFF2 <= ssFF1; - ssFF3 <= ssFF2; - -- check if slave select signal has falling edge (slave is selected by master) - if(ssFF3 = '1' and ssFF2 = '0') then - --reset counter if true - counter <= 23; - --disable data read if rising edge (slave is not selected) - elsif (ssFF3 = '0' and ssFF2 = '1') then - enable <= '0'; - end if; - --check if synchronised slave select signal is falling edge or data read is enabled - if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then - enable <= '1'; --enable data read - if (PulseFF3 = '0' and PulseFF2 = '1') then -- check for rising edge of clk SPI - if counter > -1 then - counter <= counter - 1; - -- data transfer into vector - data(counter) <= dataFF3; - end if; - end if; - --check if counter is done - if counter = -1 then - counter <= 23; --reset counter - dataRead <= data; - end if; - elsif (enable = '0') then - --dataRead <= data; - - end if; - - end if; - - end process; - + serial_peripheral_interface: component spi port map( + SYSCLK => SYSCLK, + SPI_CLK => SPI_CLK, + SPI_MOSI => SPI_MOSI, + SPI_CS => '1', + DATA => SPI_DATA); + + picture_processing_unit: component ppu port map( + CLK100 => SYSCLK, + RESET => RESET, + EN => '1', + WEN => WEN, + ADDR => SPI_DATA_ADDR, + DATA => SPI_DATA_DATA, + R => R, + G => G, + B => B, + NVSYNC => NVSYNC, + NHSYNC => NHSYNC, + TVBLANK => TVBLANK, + THBLANK => THBLANK); end Behavioral; diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 4060a21..b4b83db 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -197,14 +197,32 @@ + + + + + + + + + + + + + + + + + + @@ -298,6 +316,7 @@ + @@ -311,6 +330,7 @@ + -- cgit v1.2.3 From 148db0e330e158381bf2b5b39e139d75c55088b2 Mon Sep 17 00:00:00 2001 From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com> Date: Fri, 10 Mar 2023 16:36:21 +0100 Subject: Delete c_cpp_properties.json --- src/.vscode/c_cpp_properties.json | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 src/.vscode/c_cpp_properties.json diff --git a/src/.vscode/c_cpp_properties.json b/src/.vscode/c_cpp_properties.json deleted file mode 100644 index 359928d..0000000 --- a/src/.vscode/c_cpp_properties.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "configurations": [ - { - "name": "Linux", - "includePath": [ - "${workspaceFolder}/**" - ], - "defines": [], - "compilerPath": "/usr/bin/gcc", - "cStandard": "c17", - "cppStandard": "c++14", - "intelliSenseMode": "linux-gcc-x64" - } - ], - "version": 4 -} \ No newline at end of file -- cgit v1.2.3 From 233b2e7a0743935db145f921dd49756248aaee58 Mon Sep 17 00:00:00 2001 From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com> Date: Fri, 10 Mar 2023 16:36:38 +0100 Subject: Delete settings.json --- src/.vscode/settings.json | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 src/.vscode/settings.json diff --git a/src/.vscode/settings.json b/src/.vscode/settings.json deleted file mode 100644 index d485e2c..0000000 --- a/src/.vscode/settings.json +++ /dev/null @@ -1,6 +0,0 @@ -{ - "files.associations": { - "hh_entity.h": "c", - "maths.h": "c" - } -} \ No newline at end of file -- cgit v1.2.3 From a52a405cd9932abbc51713d75d3b91884820b081 Mon Sep 17 00:00:00 2001 From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com> Date: Fri, 10 Mar 2023 16:42:04 +0100 Subject: Delete tiles.bs --- test/bin/tiles.bs | 544 ------------------------------------------------------ 1 file changed, 544 deletions(-) delete mode 100644 test/bin/tiles.bs diff --git a/test/bin/tiles.bs b/test/bin/tiles.bs deleted file mode 100644 index 4452c2a..0000000 --- a/test/bin/tiles.bs +++ /dev/null @@ -1,544 +0,0 @@ -0000: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -0010: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -0020: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -0030: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -0040: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -0050: 01 01 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24 24 24 24 24 24 -1f00: 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e -1f10: 0d 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0d -1f20: 0d 0d 0d 0e 12 12 12 12 12 12 12 12 0e 0d 0d 0d -1f30: 0d 0d 13 0d 0e 12 12 12 12 12 12 0e 0d 13 0d 0d -1f40: 0d 0d 12 13 0d 0e 12 12 12 12 0e 0d 13 12 0d 0d -1f50: 0d 0d 12 12 13 0d 0e 12 12 0e 0d 13 12 12 0d 0d -1f60: 0d 0d 12 12 12 13 0d 0e 0e 0d 13 12 12 12 0d 0d -1f70: 0d 0d 12 12 12 12 13 0d 0d 13 12 12 12 12 0d 0d -1f80: 0d 0d 12 12 12 12 0e 0d 0d 0e 12 12 12 12 0d 0d -1f90: 0d 0d 12 12 12 0e 0d 13 13 0d 0e 12 12 12 0d 0d -1fa0: 0d 0d 12 12 0e 0d 13 12 12 13 0d 0e 12 12 0d 0d -1fb0: 0d 0d 12 0e 0d 13 12 12 12 12 13 0d 0e 12 0d 0d -1fc0: 0d 0d 0e 0d 13 12 12 12 12 12 12 13 0d 0e 0d 0d -1fd0: 0d 0d 0d 13 12 12 12 12 12 12 12 12 13 0d 0d 0d -1fe0: 0d 13 13 13 13 13 13 13 13 13 13 13 13 13 13 0d -1ff0: 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 -2000: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -2010: 01 01 2d 2d 2d 2d 2d 01 01 01 2d 2d 2d 01 01 01 -2020: 01 01 01 01 2d 01 01 01 01 2d 01 01 01 2d 01 01 -2030: 01 01 01 01 2d 01 01 01 01 2d 01 01 01 2d 01 01 -2040: 01 01 01 01 2d 01 01 01 01 2d 01 01 01 2d 01 01 -2050: 01 01 01 01 2d 01 01 01 01 2d 01 01 01 2d 01 01 -2060: 01 01 01 01 2d 01 01 01 01 01 2d 2d 2d 01 01 01 -2070: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -2080: 01 01 2d 2d 2d 2d 01 01 01 01 2d 2d 2d 01 01 01 -2090: 01 01 2d 01 01 01 2d 01 01 2d 01 01 01 2d 01 01 -20a0: 01 01 2d 01 01 01 2d 01 01 2d 01 01 01 2d 01 01 -20b0: 01 01 2d 01 01 01 2d 01 01 2d 01 01 01 2d 01 01 -20c0: 01 01 2d 01 01 01 2d 01 01 2d 01 01 01 2d 01 01 -20d0: 01 01 2d 2d 2d 2d 01 01 01 01 2d 2d 2d 01 01 01 -20e0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -20f0: 01 01 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 01 -2100: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -2110: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -2120: 01 01 01 01 01 01 17 17 17 17 01 01 01 01 01 01 -2130: 01 01 01 01 17 17 17 17 17 17 17 17 01 01 01 01 -2140: 01 01 01 17 17 17 16 17 16 17 17 17 17 01 01 01 -2150: 01 01 01 17 17 17 15 15 15 15 17 17 17 01 01 01 -2160: 01 01 17 17 17 15 16 17 16 17 17 17 17 17 01 01 -2170: 01 01 17 17 17 15 16 17 16 17 17 17 17 17 01 01 -2180: 01 01 17 17 17 15 16 17 16 17 17 17 17 17 01 01 -2190: 01 01 17 17 17 15 16 17 16 17 17 17 17 17 01 01 -21a0: 01 01 01 17 17 17 15 15 15 15 17 17 17 01 01 01 -21b0: 01 01 01 17 17 17 16 17 16 17 17 17 17 01 01 01 -21c0: 01 01 01 01 17 17 17 17 17 17 17 17 01 01 01 01 -21d0: 01 01 01 01 01 01 17 17 17 17 01 01 01 01 01 01 -21e0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -21f0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 -- cgit v1.2.3 From 635f67120132f840c825b9f9b5f4fdf2a6f250ef Mon Sep 17 00:00:00 2001 From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com> Date: Fri, 10 Mar 2023 16:42:33 +0100 Subject: removed TODO --- test/bin/test_file_read.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/test/bin/test_file_read.c b/test/bin/test_file_read.c index 6357feb..e9ece4d 100644 --- a/test/bin/test_file_read.c +++ b/test/bin/test_file_read.c @@ -16,8 +16,6 @@ void printData(uint8_t* in) { } void hh_ppu_load_tilemap() { - - //TODO: lees bestand in mem char* filename = "tiles.bin"; FILE* fp = fopen(filename,"rb"); if (!fp){ -- cgit v1.2.3 From 877ac831461f35d00e0e0ab7d6afbe93768fc7c6 Mon Sep 17 00:00:00 2001 From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com> Date: Fri, 10 Mar 2023 16:42:59 +0100 Subject: Update test_file_read.c --- test/bin/test_file_read.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/test/bin/test_file_read.c b/test/bin/test_file_read.c index e9ece4d..b3357ce 100644 --- a/test/bin/test_file_read.c +++ b/test/bin/test_file_read.c @@ -28,10 +28,7 @@ void hh_ppu_load_tilemap() { // printf("%i",_size); for (int i = 0; i < _size; i++) { uint8_t data[HH_PPU_VRAM_TMM_SPRITE_SIZE]; - // for (int i = 0; i < 255; i++) { - // buffer[i] = 0; //TODO: vullen - fread(data,HH_PPU_VRAM_TMM_SPRITE_SIZE,1,fp); - // } + fread(data,HH_PPU_VRAM_TMM_SPRITE_SIZE,1,fp); printData(data); } -- cgit v1.2.3