From 08efcdf63f78bbf78587b4d6e93d492abd4988f4 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Sat, 18 Feb 2023 15:14:50 +0100 Subject: no clock output while reset high in pceg --- basys3/basys3.srcs/ppu_pceg.vhdl | 6 +++--- basys3/basys3.xpr | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/basys3/basys3.srcs/ppu_pceg.vhdl b/basys3/basys3.srcs/ppu_pceg.vhdl index a5b86ae..9675e5b 100644 --- a/basys3/basys3.srcs/ppu_pceg.vhdl +++ b/basys3/basys3.srcs/ppu_pceg.vhdl @@ -17,9 +17,9 @@ architecture Behavioral of ppu_pceg is signal state: states := PL_SPRITE; begin -- output drivers - SPRITE <= CLK when state = PL_SPRITE else '0'; - COMP_PAL <= CLK when state = PL_COMP_PAL else '0'; - DONE <= '1' when state = PL_DONE else '0'; + SPRITE <= CLK when RESET = '0' and state = PL_SPRITE else '0'; + COMP_PAL <= CLK when RESET = '0' and state = PL_COMP_PAL else '0'; + DONE <= '1' when RESET = '0' and state = PL_DONE else '0'; process(CLK, RESET) variable CLK_IDX: natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0; diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index a08109b..1a6d509 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -59,7 +59,7 @@