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path: root/basys3/basys3.xpr
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* top.vhdllonkaars2023-03-10
* merge #16lonkaars2023-02-24
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* | ppu foreground sprite working and ~50% testedlonkaars2023-02-23
* | WIP ppu fg sprite fetch logiclonkaars2023-02-22
* | WIP foreground sprite + `std_logic_vector` -> `unsigned` messlonkaars2023-02-21
* | WIP ppu foreground sprite componentlonkaars2023-02-21
* | background sprite component done, tested, and working without latcheslonkaars2023-02-21
* | PPU debugged and working (but with unwanted latches)lonkaars2023-02-21
* | PPU background sprite component done (but unverified)lonkaars2023-02-20
* | update TMM data width + update memory map (WIP ppu_sprite_bg)lonkaars2023-02-20
* | PPU AUX memory finished and testedlonkaars2023-02-20
* | exposed ram module implementedlonkaars2023-02-20
* | rename .vhdl to .vhdlonkaars2023-02-20
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* format and add apu sources to vivado project filelonkaars2023-02-19
* finish ppu address decoderlonkaars2023-02-19
* no clock output while reset high in pceglonkaars2023-02-18
* ppu pceg done + ppu top.vhdl donelonkaars2023-02-18
* WIP ppu.vhdllonkaars2023-02-17
* initial commitlonkaars2023-02-02