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* separate constants file for vhdl codelonkaars2023-02-19
* no clock output while reset high in pceglonkaars2023-02-18
* ppu pceg done + ppu top.vhdl donelonkaars2023-02-18
* use tabs for indentationlonkaars2023-02-17
* separate AUX memory into separate componentlonkaars2023-02-17
* safety commit (before remove DI lines)lonkaars2023-02-17
* WIP ppu.vhdllonkaars2023-02-17