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Diffstat (limited to 'docs/architecture.md')
| -rw-r--r-- | docs/architecture.md | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/architecture.md b/docs/architecture.md index 4e57be0..aa66276 100644 --- a/docs/architecture.md +++ b/docs/architecture.md @@ -239,7 +239,9 @@ Important notes: This diagram describes which components use which lines during pipeline stages 0-9. The pipeline stage counter is reset after every pixel, and is run on the -system clock (100 MHz). +system clock (100 MHz). Underlined labels indicate when a signal is written, +and normal text is used to indicate a signal read. Labels with a dotted outline +are used for timing, but don't directly read/write any signals. ## Registers |