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-rw-r--r--basys3/basys3.srcs/apu_LUT_reader.vhd5
-rw-r--r--basys3/basys3.srcs/apu_tb_LUT_reader.vhd2
2 files changed, 4 insertions, 3 deletions
diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd
index e56f855..6039798 100644
--- a/basys3/basys3.srcs/apu_LUT_reader.vhd
+++ b/basys3/basys3.srcs/apu_LUT_reader.vhd
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
entity apu_LUT_reader is
port (
- clk : in std_logic;
+ clk : in std_logic;
rst : in std_logic;
freq : in std_logic_vector(11 downto 0);
wave : in std_logic_vector(1 downto 0);
@@ -27,6 +27,7 @@ begin
if rst = '1' then
idx <= x"00";
buf <= x"00";
+ value <= x"00";
elsif rising_edge(clk) then
-- main code here
@@ -34,7 +35,7 @@ begin
value <= std_logic_vector( idx );
elsif wave = "01" then -- Square
if idx < (SAMPLE_SIZE/2) then
- value <= x"00";
+ value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave)
else
value <= x"FF";
end if;
diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
index d4ed935..5a38d39 100644
--- a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
+++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
@@ -45,4 +45,4 @@ begin
end loop;
end process;
-end architecture; \ No newline at end of file
+end architecture;