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-rw-r--r--basys3/basys3.srcs/io.xdc37
-rw-r--r--basys3/basys3.srcs/ppu_dispctl.vhd12
-rw-r--r--basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci28
-rw-r--r--basys3/basys3.srcs/spi.vhd24
-rw-r--r--basys3/basys3.srcs/spi_tb.vhd385
-rw-r--r--basys3/basys3.srcs/top.vhd4
-rw-r--r--basys3/basys3.xpr21
7 files changed, 279 insertions, 232 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc
index e8e47d2..85d4fc2 100644
--- a/basys3/basys3.srcs/io.xdc
+++ b/basys3/basys3.srcs/io.xdc
@@ -4,7 +4,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
set_property PACKAGE_PIN J2 [get_ports SPI_CLK]
set_property PACKAGE_PIN C15 [get_ports SPI_CS]
-set_property PACKAGE_PIN L1 [get_ports SPI_MOSI]
+set_property PACKAGE_PIN L2 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]
set_property IOSTANDARD LVCMOS33 [get_ports RESET]
@@ -49,3 +49,38 @@ set_property PACKAGE_PIN C16 [get_ports VBLANK]
set_property PACKAGE_PIN J1 [get_ports WEN]
+
+set_property IOSTANDARD LVCMOS33 [get_ports DBG_DISP_ADDR]
+set_property PACKAGE_PIN R2 [get_ports DBG_DISP_ADDR]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[0]}]
+set_property PACKAGE_PIN L1 [get_ports {DBG_LEDS_OUT[15]}]
+set_property PACKAGE_PIN P1 [get_ports {DBG_LEDS_OUT[14]}]
+set_property PACKAGE_PIN N3 [get_ports {DBG_LEDS_OUT[13]}]
+set_property PACKAGE_PIN P3 [get_ports {DBG_LEDS_OUT[12]}]
+set_property PACKAGE_PIN U3 [get_ports {DBG_LEDS_OUT[11]}]
+set_property PACKAGE_PIN W3 [get_ports {DBG_LEDS_OUT[10]}]
+set_property PACKAGE_PIN V3 [get_ports {DBG_LEDS_OUT[9]}]
+set_property PACKAGE_PIN V13 [get_ports {DBG_LEDS_OUT[8]}]
+set_property PACKAGE_PIN V14 [get_ports {DBG_LEDS_OUT[7]}]
+set_property PACKAGE_PIN U14 [get_ports {DBG_LEDS_OUT[6]}]
+set_property PACKAGE_PIN U15 [get_ports {DBG_LEDS_OUT[5]}]
+set_property PACKAGE_PIN W18 [get_ports {DBG_LEDS_OUT[4]}]
+set_property PACKAGE_PIN V19 [get_ports {DBG_LEDS_OUT[3]}]
+set_property PACKAGE_PIN U19 [get_ports {DBG_LEDS_OUT[2]}]
+set_property PACKAGE_PIN E19 [get_ports {DBG_LEDS_OUT[1]}]
+set_property PACKAGE_PIN U16 [get_ports {DBG_LEDS_OUT[0]}]
diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
index 117b780..1d3d922 100644
--- a/basys3/basys3.srcs/ppu_dispctl.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -20,10 +20,10 @@ end ppu_dispctl;
architecture Behavioral of ppu_dispctl is
component ppu_dispctl_pixclk is port (
- clk_out1 : out std_logic;
- clk_out2 : out std_logic;
+ npxclk : out std_logic;
+ tpxclk : out std_logic;
reset : in std_logic;
- clk_in1 : in std_logic);
+ sysclk : in std_logic);
end component;
component ppu_dispctl_slbuf port( -- scanline buffer
clka : in std_logic;
@@ -159,8 +159,8 @@ begin
rstb_busy => open);
pixel_clock: component ppu_dispctl_pixclk port map(
- clk_in1 => SYSCLK,
+ sysclk => SYSCLK,
reset => RESET,
- clk_out1 => NPIXCLK,
- clk_out2 => TPIXCLK);
+ npxclk => NPIXCLK,
+ tpxclk => TPIXCLK);
end Behavioral;
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
index 620084f..2e48660 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
@@ -65,9 +65,9 @@
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
- "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
- "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
- "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+ "PRIMARY_PORT": [ { "value": "sysclk", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT1_PORT": [ { "value": "npxclk", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT2_PORT": [ { "value": "tpxclk", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
@@ -338,8 +338,8 @@
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
- "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______191.696____114.212", "resolve_type": "generated", "usage": "all" } ],
- "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2___6.25000______0.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW1": [ { "value": "__npxclk__25.00000______0.000______50.0______191.696____114.212", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW2": [ { "value": "__tpxclk___6.25000______0.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
@@ -468,10 +468,10 @@
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
- "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+ "C_PRIMARY_PORT": [ { "value": "sysclk", "resolve_type": "generated", "usage": "all" } ],
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
- "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
- "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT1_PORT": [ { "value": "npxclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT2_PORT": [ { "value": "tpxclk", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
@@ -611,9 +611,9 @@
"boundary": {
"ports": {
"reset": [ { "direction": "in", "driver_value": "0" } ],
- "clk_in1": [ { "direction": "in" } ],
- "clk_out1": [ { "direction": "out" } ],
- "clk_out2": [ { "direction": "out" } ]
+ "sysclk": [ { "direction": "in" } ],
+ "npxclk": [ { "direction": "out" } ],
+ "tpxclk": [ { "direction": "out" } ]
},
"interfaces": {
"reset": {
@@ -645,7 +645,7 @@
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
},
"port_maps": {
- "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+ "CLK_IN1": [ { "physical_name": "sysclk" } ]
}
},
"clock_CLK_OUT1": {
@@ -663,7 +663,7 @@
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
- "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+ "CLK_OUT1": [ { "physical_name": "npxclk" } ]
}
},
"clock_CLK_OUT2": {
@@ -681,7 +681,7 @@
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
- "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
+ "CLK_OUT2": [ { "physical_name": "tpxclk" } ]
}
}
}
diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd
index 1560b54..a09d5df 100644
--- a/basys3/basys3.srcs/spi.vhd
+++ b/basys3/basys3.srcs/spi.vhd
@@ -16,15 +16,15 @@ architecture Behavioral of spi is
signal clkFF0,clkFF1,clkFF2,clkFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI
signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI
- signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
- signal counter : integer := 31; -- counter for data position
-
constant COUNTER_RESET_VALUE : integer := PPU_RAM_BUS_ADDR_WIDTH + PPU_RAM_BUS_DATA_WIDTH - 1;
begin
process (SYSCLK)
+ variable bit_idx : integer range 0 to COUNTER_RESET_VALUE := COUNTER_RESET_VALUE; -- counter for data position
+ variable spi_reg : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
begin
if RESET = '1' then
- counter <= COUNTER_RESET_VALUE;
+ spi_reg := (others => '0');
+ bit_idx := COUNTER_RESET_VALUE;
DATA <= (others => '0');
elsif rising_edge(SYSCLK) then
-- flip flop for clk SPI to synchronise a
@@ -39,17 +39,15 @@ begin
dataFF3 <= dataFF2;
if (clkFF3 = '0' and clkFF2 = '1') then -- check for rising edge of clk SPI
- if counter > -1 then
- counter <= counter - 1;
- -- data transfer into vector
- SPI_REG(counter) <= dataFF3;
+ spi_reg(bit_idx) := dataFF3; -- load new data into temporary register
+
+ if bit_idx = 0 then
+ bit_idx := COUNTER_RESET_VALUE; -- reset bit index
+ DATA <= spi_reg; -- flush temporary register to data outpu
+ else
+ bit_idx := bit_idx - 1; -- decrement bit index
end if;
end if;
- -- check if counter is done
- if counter = -1 then
- counter <= COUNTER_RESET_VALUE; -- reset counter
- DATA <= SPI_REG;
- end if;
end if;
end process;
end Behavioral;
diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd
index a8aa8c2..f6e2d21 100644
--- a/basys3/basys3.srcs/spi_tb.vhd
+++ b/basys3/basys3.srcs/spi_tb.vhd
@@ -36,197 +36,200 @@ begin
spi_data: process
begin
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '0';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
-
- SPI_MOSI <= '1';
- wait for 50 ns;
- SPI_CLK <= '1';
- wait for 50 ns;
- SPI_CLK <= '0';
+ for i in 0 to 2 loop
+ -- data = 0b01010110010100001001110011111111 (0x56509cff)
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ end loop;
wait for 50 ns;
SPI_CLK <= '1';
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd
index 84ab7eb..ed1c3b0 100644
--- a/basys3/basys3.srcs/top.vhd
+++ b/basys3/basys3.srcs/top.vhd
@@ -9,6 +9,8 @@ entity top is port (
SPI_CLK : in std_logic; -- incoming clock of SPI
SPI_MOSI : in std_logic; -- incoming data of SPI
WEN : in std_logic; -- PPU VRAM write enable
+ DBG_DISP_ADDR : in std_logic; -- display address/data switch (debug)
+ DBG_LEDS_OUT : out std_logic_vector(15 downto 0); -- debug address/data output leds
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
VSYNC, HSYNC : out std_logic; -- VGA sync out
VBLANK : out std_logic); -- vblank for synchronization
@@ -44,6 +46,8 @@ begin
SPI_MOSI => SPI_MOSI,
DATA => SPI_DATA);
+ DBG_LEDS_OUT <= SPI_DATA_ADDR when DBG_DISP_ADDR = '1' else SPI_DATA_DATA;
+
picture_processing_unit: component ppu port map(
CLK100 => SYSCLK,
RESET => RESET,
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 5b31f27..82d7be5 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -59,20 +59,20 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
- <Option Name="WTXSimLaunchSim" Val="5"/>
+ <Option Name="WTXSimLaunchSim" Val="19"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="0"/>
- <Option Name="WTModelSimExportSim" Val="0"/>
- <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="1"/>
+ <Option Name="WTModelSimExportSim" Val="1"/>
+ <Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="0"/>
- <Option Name="WTVcsExportSim" Val="0"/>
- <Option Name="WTRivieraExportSim" Val="0"/>
- <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="1"/>
+ <Option Name="WTRivieraExportSim" Val="1"/>
+ <Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -209,6 +209,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/ppu_comp_tb.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="spi_tb"/>