diff options
Diffstat (limited to 'basys3')
| -rw-r--r-- | basys3/basys3.srcs/ppu_consts.vhd | 10 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl.vhd | 123 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl_demo_top.vhd | 32 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl_tb.vhd | 14 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_dispctl_test_img/ppu_dispctl_test_img.xci | 254 | ||||
| -rw-r--r-- | basys3/basys3.xpr | 45 |
6 files changed, 373 insertions, 105 deletions
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd index 8e9b494..4784950 100644 --- a/basys3/basys3.srcs/ppu_consts.vhd +++ b/basys3/basys3.srcs/ppu_consts.vhd @@ -52,15 +52,15 @@ package ppu_consts is constant PPU_PL_TOTAL_STAGES : natural := 14; -- VGA signal timings (https://tomverbeure.github.io/video_timings_calculator) constant PPU_VGA_H_ACTIVE : natural := PPU_NATIVE_SCREEN_WIDTH; - constant PPU_VGA_H_PORCH_FRONT : natural := 8; - constant PPU_VGA_H_SYNC : natural := 96; - constant PPU_VGA_H_PORCH_BACK : natural := 40; + constant PPU_VGA_H_PORCH_FRONT : natural := 96; + constant PPU_VGA_H_SYNC : natural := 16; + constant PPU_VGA_H_PORCH_BACK : natural := 48; constant PPU_VGA_H_BLANK : natural := PPU_VGA_H_PORCH_FRONT + PPU_VGA_H_SYNC + PPU_VGA_H_PORCH_BACK; constant PPU_VGA_H_TOTAL : natural := PPU_VGA_H_BLANK + PPU_VGA_H_ACTIVE; constant PPU_VGA_V_ACTIVE : natural := PPU_NATIVE_SCREEN_HEIGHT; - constant PPU_VGA_V_PORCH_FRONT : natural := 2; + constant PPU_VGA_V_PORCH_FRONT : natural := 10; constant PPU_VGA_V_SYNC : natural := 2; - constant PPU_VGA_V_PORCH_BACK : natural := 25; + constant PPU_VGA_V_PORCH_BACK : natural := 29; constant PPU_VGA_V_BLANK : natural := PPU_VGA_V_PORCH_FRONT + PPU_VGA_V_SYNC + PPU_VGA_V_PORCH_BACK; constant PPU_VGA_V_TOTAL : natural := PPU_VGA_V_BLANK + PPU_VGA_V_ACTIVE; constant PPU_VGA_SIGNAL_PIXEL_IDX_MAX : natural := PPU_VGA_V_TOTAL * PPU_VGA_H_TOTAL; -- horizontal and vertical pixel clock index diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd index b03ea3f..1be0365 100644 --- a/basys3/basys3.srcs/ppu_dispctl.vhd +++ b/basys3/basys3.srcs/ppu_dispctl.vhd @@ -48,15 +48,56 @@ architecture Behavioral of ppu_dispctl is signal U_POS_Y : unsigned(PPU_SCREEN_T_POS_Y_WIDTH-1 downto 0) := (others => '0'); -- upscaled tiny y position signal N_POS_X : unsigned(PPU_SCREEN_N_POS_X_WIDTH-1 downto 0) := (others => '0'); -- native x position signal N_POS_Y : unsigned(PPU_SCREEN_N_POS_Y_WIDTH-1 downto 0) := (others => '0'); -- native y position - signal TMP_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0'); -- tiny screen pixel x - signal TMP_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0'); -- tiny screen pixel y - signal TMP_RO, TMP_GO, TMP_BO : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color out - signal TMP_THBLANK, TMP_TVBLANK : std_logic := '0'; -- tiny sync signals signal NACTIVE, NHACTIVE, NVACTIVE : std_logic := '0'; signal TACTIVE, THACTIVE, TVACTIVE : std_logic := '0'; begin - -- native (TODO: +upscaled) VCOUNT and HCOUNT + -- tiny VCOUNT and HCOUNT + process(TPIXCLK, RESET) + variable TMP_THCOUNT, TMP_TVCOUNT : unsigned(PPU_VGA_SIGNAL_PIXEL_WIDTH-1 downto 0) := (others => '0'); + variable TMP_THBLANK, TMP_TVBLANK : std_logic := '0'; + begin + TVCOUNT <= TMP_TVCOUNT; + THCOUNT <= TMP_THCOUNT; + + T_POS_X <= resize(TMP_THCOUNT - (PPU_VGA_H_PORCH_BACK / 4), T_POS_X'length) when N_POS_Y(0) = to_unsigned(PPU_VGA_V_PORCH_BACK, 1)(0) else + resize(TMP_THCOUNT - ((PPU_VGA_H_PORCH_BACK + PPU_VGA_H_BLANK) / 4), T_POS_X'length); -- divide tiny x equally over two native scanlines + T_POS_Y <= resize(TMP_TVCOUNT - (PPU_VGA_V_PORCH_BACK / 2), T_POS_Y'length); + + THBLANK <= TMP_THBLANK; + TVBLANK <= TMP_TVBLANK; + + -- scanline buffer data in + DATA_I <= RI & GI & BI; + ADDR_I <= std_logic_vector(resize(T_POS_X, ADDR_I'length)) when T_POS_Y(0) = '0' else std_logic_vector(resize(T_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH); + + if RESET = '1' then + TMP_THCOUNT := (others => '0'); + TMP_TVCOUNT := (others => '0'); + TMP_THBLANK := '0'; + TMP_TVBLANK := '0'; + elsif rising_edge(TPIXCLK) then + TMP_THCOUNT := TMP_THCOUNT + 1; + if TMP_THCOUNT >= PPU_VGA_H_TOTAL then + TMP_THCOUNT := (others => '0'); + + TMP_TVCOUNT := TMP_TVCOUNT + 1; + if TMP_TVCOUNT >= PPU_VGA_V_TOTAL then + TMP_TVCOUNT := (others => '0'); + end if; + + -- vertical display area (active) + if TMP_TVCOUNT = PPU_VGA_V_PORCH_BACK then TMP_TVBLANK := '0'; end if; + if TMP_TVCOUNT = PPU_VGA_V_PORCH_BACK + PPU_VGA_V_ACTIVE then TMP_TVBLANK := '1'; end if; + end if; + + -- horizontal display area (active) + if TMP_THCOUNT = PPU_VGA_H_PORCH_BACK then TMP_THBLANK := '0'; end if; + if TMP_THCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE then TMP_THBLANK := '1'; end if; + end if; + end process; + + -- native (+upscaled) VCOUNT and HCOUNT process(NPIXCLK, RESET) variable TMP_NHCOUNT, TMP_NVCOUNT : unsigned(PPU_VGA_SIGNAL_PIXEL_WIDTH-1 downto 0) := (others => '0'); variable TMP_NHACTIVE, TMP_NVACTIVE : std_logic := '0'; @@ -71,6 +112,14 @@ begin NHSYNC <= TMP_NHSYNC; N_POS_X <= resize(TMP_NHCOUNT - PPU_VGA_H_PORCH_BACK, N_POS_X'length) when TMP_NHACTIVE = '1' else (others => '0'); N_POS_Y <= resize(TMP_NVCOUNT - PPU_VGA_V_PORCH_BACK, N_POS_Y'length) when TMP_NVACTIVE = '1' else (others => '0'); + U_POS_X <= resize(N_POS_X(N_POS_X'length-1 downto 1), U_POS_X'length); + U_POS_Y <= resize(N_POS_Y(N_POS_Y'length-1 downto 1), U_POS_Y'length); + + -- scanline buffer data out + ADDR_O <= std_logic_vector(resize(U_POS_X, ADDR_I'length)) when U_POS_Y(0) = '0' else std_logic_vector(resize(U_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH); + RO <= DATA_O(11 downto 8) when NACTIVE = '1' else (others => '0'); + GO <= DATA_O(7 downto 4) when NACTIVE = '1' else (others => '0'); + BO <= DATA_O(3 downto 0) when NACTIVE = '1' else (others => '0'); if RESET = '1' then TMP_NHCOUNT := (others => '0'); @@ -110,47 +159,8 @@ begin end if; end process; - -- tiny VCOUNT and HCOUNT - process(TPIXCLK, RESET) - variable TMP_THCOUNT, TMP_TVCOUNT: unsigned(PPU_VGA_SIGNAL_PIXEL_WIDTH-1 downto 0) := (others => '0'); - begin - TVCOUNT <= TMP_TVCOUNT; - THCOUNT <= TMP_THCOUNT; - if RESET = '1' then - TMP_THCOUNT := (others => '0'); - TMP_TVCOUNT := (others => '0'); - elsif rising_edge(TPIXCLK) then - TMP_THCOUNT := TMP_THCOUNT + 1; - if TMP_THCOUNT >= PPU_VGA_H_TOTAL then - TMP_THCOUNT := (others => '0'); - - TMP_TVCOUNT := TMP_TVCOUNT + 1; - if TMP_TVCOUNT >= PPU_VGA_V_TOTAL then - TMP_TVCOUNT := (others => '0'); - end if; - end if; - end if; - end process; - - -- T_POS_X <= resize(THCOUNT - (PPU_VGA_H_PORCH_BACK / 4), T_POS_X'length) when N_POS_Y(0) = to_unsigned(PPU_VGA_V_PORCH_BACK, 1)(0) else - -- resize(THCOUNT - ((PPU_VGA_H_PORCH_BACK + PPU_VGA_H_BLANK) / 4), T_POS_X'length); -- divide tiny x equally over two native scanlines - -- T_POS_Y <= resize(TVCOUNT - (PPU_VGA_V_PORCH_BACK / 2), T_POS_Y'length); - - -- DATA_I <= RI & GI & BI; - -- ADDR_I <= std_logic_vector(resize(T_POS_X, ADDR_I'length)) when T_POS_Y(0) = '0' else std_logic_vector(resize(T_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH); - - -- TMP_X <= std_logic_vector(T_POS_X) when NACTIVE = '1' else (others => '0'); - -- TMP_Y <= std_logic_vector(T_POS_Y) when NACTIVE = '1' else (others => '0'); - - U_POS_X <= resize(N_POS_X(N_POS_X'length-1 downto 1), U_POS_X'length); - U_POS_Y <= resize(N_POS_Y(N_POS_Y'length-1 downto 1), U_POS_Y'length); - -- U_POS_X <= resize(N_POS_X / 2, U_POS_X'length); - -- U_POS_Y <= resize(N_POS_Y / 2, U_POS_Y'length); - - ADDR_O <= std_logic_vector(resize(U_POS_X, ADDR_I'length)) when U_POS_Y(0) = '0' else std_logic_vector(resize(U_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH); - TMP_RO <= DATA_O(11 downto 8) when NACTIVE = '1' else (others => '0'); - TMP_GO <= DATA_O(7 downto 4) when NACTIVE = '1' else (others => '0'); - TMP_BO <= DATA_O(3 downto 0) when NACTIVE = '1' else (others => '0'); + X <= std_logic_vector(T_POS_X) when NACTIVE = '1' else (others => '0'); + Y <= std_logic_vector(T_POS_Y) when NACTIVE = '1' else (others => '0'); scanline_buffer : component ppu_dispctl_slbuf port map( clka => SYSCLK, @@ -169,25 +179,4 @@ begin reset => RESET, clk_out1 => NPIXCLK, clk_out2 => TPIXCLK); - - process(NPIXCLK, RESET) - begin - if RESET = '1' then - X <= (others => '0'); - Y <= (others => '0'); - RO <= (others => '0'); - GO <= (others => '0'); - BO <= (others => '0'); - THBLANK <= '0'; - TVBLANK <= '0'; - elsif rising_edge(NPIXCLK) then - X <= TMP_X; - Y <= TMP_Y; - RO <= TMP_RO; - GO <= TMP_GO; - BO <= TMP_BO; - THBLANK <= TMP_THBLANK; - TVBLANK <= TMP_TVBLANK; - end if; - end process; end Behavioral; diff --git a/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd b/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd index b8df3c0..9a0643e 100644 --- a/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd +++ b/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd @@ -2,6 +2,8 @@ library ieee; library work; use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; use work.ppu_consts.all; entity ppu_dispctl_demo is port( @@ -25,16 +27,36 @@ architecture Behavioral of ppu_dispctl_demo is NVSYNC, NHSYNC : out std_logic; -- VGA sync out THBLANK, TVBLANK : out std_logic); -- tiny sync signals end component; + component ppu_dispctl_test_img port ( + clka : in std_logic; + addra : in std_logic_vector (16 downto 0); + douta : out std_logic_vector (11 downto 0)); + end component; + signal ADDR : std_logic_vector (16 downto 0); + signal DATA : std_logic_vector (11 downto 0); + signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + + alias DATA_R is DATA(11 downto 8); + alias DATA_G is DATA(7 downto 4); + alias DATA_B is DATA(3 downto 0); begin + ADDR <= std_logic_vector(resize(unsigned(X) + unsigned(Y) * to_unsigned(PPU_SCREEN_WIDTH, ADDR'length), ADDR'length)); + + test_img : component ppu_dispctl_test_img port map( + clka => CLK100, + addra => ADDR, + douta => DATA); + display_controller : component ppu_dispctl port map( SYSCLK => CLK100, RESET => RESET, PREADY => '1', - X => open, - Y => open, - RI => (others => '1'), - GI => (others => '0'), - BI => (others => '1'), + X => X, + Y => Y, + RI => DATA_R, + GI => DATA_G, + BI => DATA_B, RO => R, GO => G, BO => B, diff --git a/basys3/basys3.srcs/ppu_dispctl_tb.vhd b/basys3/basys3.srcs/ppu_dispctl_tb.vhd index deb3d48..e54a304 100644 --- a/basys3/basys3.srcs/ppu_dispctl_tb.vhd +++ b/basys3/basys3.srcs/ppu_dispctl_tb.vhd @@ -14,8 +14,6 @@ architecture behavioral of ppu_dispctl_tb is signal RESET : std_logic := '0'; signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0'); signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0'); - signal RI,GI,BI : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); - signal PREADY : std_logic := '0'; signal RO,GO,BO : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); signal NVSYNC, NHSYNC : std_logic := '0'; signal THBLANK, TVBLANK : std_logic := '0'; @@ -23,12 +21,12 @@ begin uut : entity work.ppu_dispctl port map( SYSCLK => SYSCLK, RESET => RESET, - PREADY => PREADY, + PREADY => '1', X => X, Y => Y, - RI => RI, - GI => GI, - BI => BI, + RI => (others => '1'), + GI => (others => '0'), + BI => (others => '1'), RO => RO, GO => GO, BO => BO, @@ -40,9 +38,9 @@ begin process begin for i in 0 to 3200000 loop - wait for 5 ps; + wait for 5 ns; SYSCLK <= '1'; - wait for 5 ps; + wait for 5 ns; SYSCLK <= '0'; end loop; wait; -- stop for simulator diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_test_img/ppu_dispctl_test_img.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_test_img/ppu_dispctl_test_img.xci new file mode 100644 index 0000000..f6ddeb4 --- /dev/null +++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_test_img/ppu_dispctl_test_img.xci @@ -0,0 +1,254 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ppu_dispctl_test_img", + "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", + "ip_revision": "5", + "gen_directory": "../../../../basys3.gen/sources_1/ip/ppu_dispctl_test_img", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ppu_dispctl_test_img", "resolve_type": "user", "usage": "all" } ], + "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], + "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ], + "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ], + "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ], + "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Write_Width_A": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Write_Depth_A": [ { "value": "76800", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Read_Width_A": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Write_Width_B": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_B": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Coe_File": [ { "value": "../../../../../test/upscaler/img.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { 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"access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +}
\ No newline at end of file diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 3fc95b5..a277fdc 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -61,20 +61,20 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="232"/> + <Option Name="WTXSimLaunchSim" Val="244"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="15"/> - <Option Name="WTModelSimExportSim" Val="15"/> - <Option Name="WTQuestaExportSim" Val="15"/> + <Option Name="WTXSimExportSim" Val="17"/> + <Option Name="WTModelSimExportSim" Val="17"/> + <Option Name="WTQuestaExportSim" Val="17"/> <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="15"/> - <Option Name="WTRivieraExportSim" Val="15"/> - <Option Name="WTActivehdlExportSim" Val="15"/> + <Option Name="WTVcsExportSim" Val="17"/> + <Option Name="WTRivieraExportSim" Val="17"/> + <Option Name="WTActivehdlExportSim" Val="17"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="XSimRadix" Val="hex"/> <Option Name="XSimTimeUnit" Val="ns"/> @@ -111,6 +111,19 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PPRDIR/../test/upscaler/img.coe"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/ip/ppu_dispctl_test_img/ppu_dispctl_test_img.xci"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="ppu_dispctl_demo"/> @@ -151,7 +164,7 @@ <Option Name="PamPseudoTop" Val="pseudo_tb"/> <Option Name="SrcSet" Val="sources_1"/> <Option Name="Incremental" Val="0"/> - <Option Name="xsim.simulate.runtime" Val="100 us"/> + <Option Name="xsim.simulate.runtime" Val="16 ms"/> </Config> </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> @@ -250,9 +263,7 @@ <Runs Version="1" Minor="19"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu_dispctl_demo.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"> <Option Id="FlattenHierarchy">0</Option> </Step> @@ -312,9 +323,7 @@ </Run> <Run Id="ppu_dispctl_pixclk_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_pixclk" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_pixclk_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> @@ -324,9 +333,7 @@ </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> @@ -395,9 +402,7 @@ </Run> <Run Id="ppu_dispctl_pixclk_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_pixclk_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> |