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-rw-r--r--basys3/basys3.srcs/apu_LUT_reader.vhd69
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency.vhd44
-rw-r--r--basys3/basys3.srcs/apu_tb_LUT_reader.vhd48
3 files changed, 141 insertions, 20 deletions
diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd
new file mode 100644
index 0000000..6039798
--- /dev/null
+++ b/basys3/basys3.srcs/apu_LUT_reader.vhd
@@ -0,0 +1,69 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity apu_LUT_reader is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ freq : in std_logic_vector(11 downto 0);
+ wave : in std_logic_vector(1 downto 0);
+ value : out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture Behavioral of apu_LUT_reader is
+
+ constant AMPLITUDE : natural := 0;
+ constant SAMPLE_SIZE : natural := 256;
+
+ signal idx : unsigned := (others => '0');
+ signal buf : unsigned := (others => '0');
+
+begin
+
+ process (clk)
+ begin
+ if rst = '1' then
+ idx <= x"00";
+ buf <= x"00";
+ value <= x"00";
+ elsif rising_edge(clk) then
+ -- main code here
+
+ if wave = "00" then -- Sawtooth
+ value <= std_logic_vector( idx );
+ elsif wave = "01" then -- Square
+ if idx < (SAMPLE_SIZE/2) then
+ value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave)
+ else
+ value <= x"FF";
+ end if;
+ elsif wave = "10" then -- Triangle
+ if idx < (SAMPLE_SIZE/2) then
+ value <= std_logic_vector( idx*2 );
+ else
+ value <= std_logic_vector( (SAMPLE_SIZE-idx)*2 );
+ end if;
+ else-- wave = "11" then -- Noise
+ -- TODO: implement noise function here:
+ value <= x"80"; -- remove this
+ end if;
+
+
+
+ if buf < unsigned(freq) then -- change frequency
+ buf <= buf + 1;
+ else
+ buf <= x"00";
+ if idx < (SAMPLE_SIZE-1) then -- moves to next index value
+ idx <= idx + 1;
+ else
+ idx <= x"00";
+ end if;
+ end if;
+
+ end if;
+ end process;
+
+end architecture;
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 7e02c75..8a7b3d6 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -5,31 +5,35 @@ use ieee.numeric_std.all;
entity apu_note_to_frequency is port (
-- clk : in std_logic;
-- rst : in std_logic;
- data : in std_logic_vector(7 downto 0);
- freq : out std_logic_vector(11 downto 0)); --frequency
+ data : in std_logic_vector(6 downto 0);
+ freq : out std_logic_vector(11 downto 0)); -- frequency
end entity;
architecture Behavioral of apu_note_to_frequency is
signal buff_small: std_logic_vector(7 downto 0) := (others => '0');
- signal buff: std_logic_vector(15 downto 0) := (others => '0');
+ signal buff: std_logic_vector(11 downto 0) := (others => '0');
signal shift: integer;
begin
- shift <= to_integer(unsigned(data(2 downto 0)));
- buff_small <=
- x"f0" when data(7 downto 3) = (x"c" & '0') else -- C 496
- x"d0" when data(7 downto 3) = (x"c" & '1') else -- C# 464
- x"b0" when data(7 downto 3) = (x"d" & '0') else -- D 432
- x"a0" when data(7 downto 3) = (x"d" & '1') else -- D# 416
- x"80" when data(7 downto 3) = (x"e" & '0') else -- E 384
- x"70" when data(7 downto 3) = (x"f" & '0') else -- F 368
- x"58" when data(7 downto 3) = (x"f" & '1') else -- F# 344
- x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320
- x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304
- x"20" when data(7 downto 3) = (x"a" & '0') else -- A 288
- x"10" when data(7 downto 3) = (x"a" & '1') else -- A# 272
- x"00" when data(7 downto 3) = (x"b" & '0') else -- B 256
- x"01";
- buff <= x"1" & buff_small;
- freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2)
+ shift <= to_integer(unsigned( data(2 downto 0) ));
+
+ buff <=
+ x"1F0" when data(6 downto 3) = (x"1") else -- C 496
+ x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464
+ x"1B0" when data(6 downto 3) = (x"3") else -- D 432
+ x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416
+ x"180" when data(6 downto 3) = (x"5") else -- E 384
+ x"170" when data(6 downto 3) = (x"6") else -- F 368
+ x"158" when data(6 downto 3) = (x"7") else -- F#/Gb 344
+ x"140" when data(6 downto 3) = (x"8") else -- G 320
+ x"130" when data(6 downto 3) = (x"9") else -- G#/Ab 304
+ x"120" when data(6 downto 3) = (x"A") else -- A 288
+ x"110" when data(6 downto 3) = (x"B") else -- A#/Bb 272
+ x"100" when data(6 downto 3) = (x"C") else -- B 256
+ x"000";
+
+ -- buff <= x"1" & buff_small;
+ freq <= std_logic_vector( shift_right(unsigned(buff), shift) );
+ -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');)
+
end architecture;
diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
new file mode 100644
index 0000000..5a38d39
--- /dev/null
+++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity apu_tb_LUT_reader is
+end entity;
+
+architecture Behavioral of apu_tb_LUT_reader is
+ component apu_LUT_reader is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ freq : in std_logic_vector(11 downto 0);
+ wave : in std_logic_vector(1 downto 0);
+ value : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ signal OK : boolean := false;
+
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal freq : std_logic_vector(11 downto 0) := (others => '0');
+ signal wave : std_logic_vector(1 downto 0) := (others => '0');
+
+begin
+
+ TB: process
+ begin
+ wave <= "00";
+ for I in 0 to 255 loop
+ clk <= '1';
+
+ -- freq <= '1';
+
+
+ wait for 1 ps;
+ clk <= '0';
+ wait for 1 ps;
+
+
+ end loop;
+ end process;
+
+end architecture;