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-rw-r--r--basys3/basys3.srcs/er_ram.vhd53
-rw-r--r--basys3/basys3.srcs/er_ram_mod.vhd34
-rw-r--r--basys3/basys3.srcs/er_ram_mod_tb.vhd81
-rw-r--r--basys3/basys3.srcs/er_ram_tb.vhd116
-rw-r--r--basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci2
-rw-r--r--basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci2
-rw-r--r--basys3/basys3.xpr49
7 files changed, 325 insertions, 12 deletions
diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd
new file mode 100644
index 0000000..a35514c
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram.vhd
@@ -0,0 +1,53 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity er_ram is -- exposed register RAM
+ generic(
+ ADDR_W : natural := 2; -- ADDR line width
+ DATA_W : natural := 2; -- DATA line width
+ ADDR_LOW : natural := 16#0000#; -- starting address
+ ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
+ port(
+ CLK : in std_logic; -- clock
+ RST : in std_logic; -- async memory clear
+ WEN : in std_logic; -- write enable
+ ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- address line
+ DATA : in std_logic_vector(DATA_W-1 downto 0); -- data input
+ REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0)); -- exposed register output
+end er_ram;
+
+architecture Behavioral of er_ram is
+ component er_ram_mod
+ generic(
+ W : natural := 1; -- module data width
+ ADDR_W : natural := 1; -- address width
+ ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+ port(
+ CLK : in std_logic; -- clock
+ RST : in std_logic; -- async memory clear
+ WEN : in std_logic; -- write enable
+ ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+ DATA : in std_logic_vector(W-1 downto 0); -- data
+ REG : out std_logic_vector(W-1 downto 0)); -- direct register out
+ end component;
+ signal INT_REG : std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0);
+begin
+ REG <= INT_REG;
+
+ registers : for idx in ADDR_LOW to ADDR_LOW + ADDR_RANGE - 1 generate
+ reg : component er_ram_mod
+ generic map(
+ W => DATA_W,
+ ADDR_W => ADDR_W,
+ ADDR_M => std_logic_vector(to_unsigned(idx, ADDR_W)))
+ port map(
+ CLK => CLK,
+ RST => RST,
+ WEN => WEN,
+ ADDR => ADDR,
+ DATA => DATA,
+ REG => INT_REG(idx*DATA_W+DATA_W-1 downto idx*DATA_W));
+ end generate;
+end Behavioral;
diff --git a/basys3/basys3.srcs/er_ram_mod.vhd b/basys3/basys3.srcs/er_ram_mod.vhd
new file mode 100644
index 0000000..ae680b1
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_mod.vhd
@@ -0,0 +1,34 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+
+entity er_ram_mod is -- exposed register RAM module (single register)
+ generic(
+ W : natural := 1; -- module data width
+ ADDR_W : natural := 1; -- address width
+ ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+ port(
+ CLK : in std_logic; -- clock
+ RST : in std_logic; -- async memory clear
+ WEN : in std_logic; -- write enable
+ ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- RAM address line
+ DATA : in std_logic_vector(W-1 downto 0); -- RAM input data line
+ REG : out std_logic_vector(W-1 downto 0)); -- direct register output lines
+end er_ram_mod;
+
+architecture Behavioral of er_ram_mod is
+ signal DATA_REG : std_logic_vector(W-1 downto 0);
+begin
+ REG <= DATA_REG;
+
+ process(CLK, RST)
+ begin
+ if RST = '1' then
+ DATA_REG <= (others => '0');
+ elsif rising_edge(CLK) then
+ if WEN = '1' and ADDR = ADDR_M then
+ DATA_REG <= DATA;
+ end if;
+ end if;
+ end process;
+end Behavioral;
diff --git a/basys3/basys3.srcs/er_ram_mod_tb.vhd b/basys3/basys3.srcs/er_ram_mod_tb.vhd
new file mode 100644
index 0000000..aa77a56
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_mod_tb.vhd
@@ -0,0 +1,81 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity er_ram_mod_tb is
+end er_ram_mod_tb;
+
+architecture behavioral of er_ram_mod_tb is
+ component er_ram_mod
+ generic(
+ W : natural := 1; -- module data width
+ ADDR_W : natural := 1; -- address width
+ ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+ port(
+ CLK : in std_logic; -- clock
+ RST : in std_logic; -- async memory clear
+ WEN : in std_logic; -- write enable
+ ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+ DATA : in std_logic_vector(W-1 downto 0); -- data
+ REG : out std_logic_vector(W-1 downto 0)); -- direct register out
+ end component;
+
+ signal CLK, RST, WEN : std_logic := '0';
+ signal ADDR : std_logic_vector(3 downto 0);
+ signal DATA : std_logic_vector(7 downto 0);
+ signal REG : std_logic_vector(7 downto 0);
+begin
+ uut : component er_ram_mod
+ generic map(
+ W => 8,
+ ADDR_W => 4,
+ ADDR_M => x"5")
+ port map(
+ CLK => CLK,
+ RST => RST,
+ WEN => WEN,
+ ADDR => ADDR,
+ DATA => DATA,
+ REG => REG);
+
+ tb : process
+ begin
+ wait for 5 ns;
+
+ -- async reset (safety)
+ RST <= '1';
+ wait for 5 ns;
+ RST <= '0';
+ wait for 5 ns;
+
+ -- set 0xef at address 0x5 (exists)
+ DATA <= x"ef";
+ ADDR <= x"5";
+ WEN <= '1';
+
+ CLK <= '1';
+ wait for 5 ns;
+ CLK <= '0';
+ wait for 5 ns;
+
+ -- set 0x34 at address 0x4 (doesn't exist)
+ ADDR <= x"4";
+ DATA <= x"34";
+
+ CLK <= '1';
+ wait for 5 ns;
+ CLK <= '0';
+ wait for 5 ns;
+
+ -- reset
+ RST <= '1';
+ wait for 5 ns;
+ RST <= '0';
+ wait for 5 ns;
+
+ wait; -- stop for simulator
+ end process;
+end;
diff --git a/basys3/basys3.srcs/er_ram_tb.vhd b/basys3/basys3.srcs/er_ram_tb.vhd
new file mode 100644
index 0000000..d360442
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_tb.vhd
@@ -0,0 +1,116 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity er_ram_tb is
+end er_ram_tb;
+
+architecture behavioral of er_ram_tb is
+ component er_ram
+ generic(
+ ADDR_W : natural := 2; -- ADDR line width
+ DATA_W : natural := 2; -- DATA line width
+ ADDR_LOW : natural := 16#0000#; -- starting address
+ ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
+ port(
+ CLK : in std_logic; -- clock
+ RST : in std_logic; -- async memory clear
+ WEN : in std_logic; -- write enable
+ ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+ DATA : in std_logic_vector(DATA_W-1 downto 0);
+ REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0));
+ end component;
+
+ signal CLK, RST, WEN : std_logic := '0';
+ signal ADDR : std_logic_vector(3 downto 0);
+ signal DATA : std_logic_vector(7 downto 0);
+ signal REG : std_logic_vector(31 downto 0);
+begin
+ uut : component er_ram
+ generic map(
+ ADDR_W => 4,
+ DATA_W => 8,
+ ADDR_LOW => 0,
+ ADDR_RANGE => 4)
+ port map(
+ CLK => CLK,
+ RST => RST,
+ WEN => WEN,
+ ADDR => ADDR,
+ DATA => DATA,
+ REG => REG);
+
+ tb : process
+ begin
+ wait for 5 ns;
+
+ -- async reset (safety)
+ RST <= '1';
+ wait for 5 ns;
+ RST <= '0';
+ wait for 5 ns;
+
+ -- set 0xef at address 0x1 (exists)
+ DATA <= x"ef";
+ ADDR <= x"1";
+ WEN <= '1';
+
+ CLK <= '1';
+ wait for 5 ns;
+ CLK <= '0';
+ wait for 5 ns;
+
+ -- set 0x34 at address 0x4 (doesn't exist)
+ ADDR <= x"4";
+ DATA <= x"34";
+
+ CLK <= '1';
+ wait for 5 ns;
+ CLK <= '0';
+ wait for 5 ns;
+
+ -- reset
+ RST <= '1';
+ wait for 5 ns;
+ RST <= '0';
+ wait for 5 ns;
+
+ -- set REG to 0x12345678
+ ADDR <= x"0";
+ DATA <= x"12";
+
+ CLK <= '1';
+ wait for 1 ns;
+ CLK <= '0';
+ wait for 1 ns;
+
+ ADDR <= x"1";
+ DATA <= x"34";
+
+ CLK <= '1';
+ wait for 1 ns;
+ CLK <= '0';
+ wait for 1 ns;
+
+ ADDR <= x"2";
+ DATA <= x"56";
+
+ CLK <= '1';
+ wait for 1 ns;
+ CLK <= '0';
+ wait for 1 ns;
+
+ ADDR <= x"3";
+ DATA <= x"78";
+
+ CLK <= '1';
+ wait for 1 ns;
+ CLK <= '0';
+ wait for 1 ns;
+
+ wait; -- stop for simulator
+ end process;
+end;
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
index f5e1696..e299ea1 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
@@ -163,7 +163,7 @@
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7a35t" } ],
"PACKAGE": [ { "value": "cpg236" } ],
- "PREFHDL": [ { "value": "VERILOG" } ],
+ "PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
index 51914b1..24d2b58 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
@@ -163,7 +163,7 @@
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7a35t" } ],
"PACKAGE": [ { "value": "cpg236" } ],
- "PREFHDL": [ { "value": "VERILOG" } ],
+ "PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index d5ba760..a63514c 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -42,6 +42,7 @@
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
@@ -60,7 +61,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
- <Option Name="WTXSimLaunchSim" Val="12"/>
+ <Option Name="WTXSimLaunchSim" Val="15"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -98,19 +99,19 @@
</FileInfo>
</File>
<File Path="$PSRCDIR/ppu_pceg.vhd">
- <FileInfo>
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/ppu.vhd">
- <FileInfo>
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/ppu_addr_dec.vhd">
- <FileInfo>
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -129,9 +130,21 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/er_ram.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/er_ram_mod.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="ppu"/>
+ <Option Name="TopModule" Val="er_ram"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
</Config>
</FileSet>
@@ -144,13 +157,13 @@
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/ppu_addr_dec_tb.vhd">
- <FileInfo>
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/ppu_pceg_tb.vhd">
- <FileInfo>
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -162,9 +175,21 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/er_ram_mod_tb.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/er_ram_tb.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="ppu_addr_dec_tb"/>
+ <Option Name="TopModule" Val="er_ram_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@@ -233,7 +258,9 @@
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
@@ -262,7 +289,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>