aboutsummaryrefslogtreecommitdiff
path: root/basys3/basys3.srcs
diff options
context:
space:
mode:
Diffstat (limited to 'basys3/basys3.srcs')
-rw-r--r--basys3/basys3.srcs/io.xdc7
-rw-r--r--basys3/basys3.srcs/spi.vhd78
-rw-r--r--basys3/basys3.srcs/spi_tb.vhd259
-rw-r--r--basys3/basys3.srcs/top.vhd5
4 files changed, 296 insertions, 53 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc
index a537742..e8e47d2 100644
--- a/basys3/basys3.srcs/io.xdc
+++ b/basys3/basys3.srcs/io.xdc
@@ -2,9 +2,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
-set_property PACKAGE_PIN A15 [get_ports SPI_CLK]
+set_property PACKAGE_PIN J2 [get_ports SPI_CLK]
set_property PACKAGE_PIN C15 [get_ports SPI_CS]
-set_property PACKAGE_PIN A17 [get_ports SPI_MOSI]
+set_property PACKAGE_PIN L1 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]
set_property IOSTANDARD LVCMOS33 [get_ports RESET]
@@ -46,5 +46,6 @@ set_property IOSTANDARD LVCMOS33 [get_ports VBLANK]
set_property IOSTANDARD LVCMOS33 [get_ports WEN]
set_property PACKAGE_PIN C16 [get_ports VBLANK]
-set_property PACKAGE_PIN A14 [get_ports WEN]
+set_property PACKAGE_PIN J1 [get_ports WEN]
+
diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd
index cdf7d4a..1560b54 100644
--- a/basys3/basys3.srcs/spi.vhd
+++ b/basys3/basys3.srcs/spi.vhd
@@ -6,65 +6,49 @@ use work.ppu_consts.all;
entity spi is port (
SYSCLK : in std_logic; -- clock basys3 100MHz
- SPI_CLK : in std_logic; -- incoming clock of SPI
+ SPI_CLK : in std_logic; -- incoming clock of SPI
SPI_MOSI : in std_logic; -- incoming data of SPI
- SPI_CS : in std_logic; -- incoming select of SPI
- DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read
+ RESET : in std_logic; -- async reset
+ DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0')); -- data read
end spi;
architecture Behavioral of spi is
- signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI
- signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI
- signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0'; -- signal for metastability synchronizer of slave select SPI
-
- signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); -- signal to store incomming data of dataSPI (2x 8bit)
- signal counter : integer := 23; -- counter for data position
- signal enable : std_logic := '0'; -- enable signal if slave is selected
+ signal clkFF0,clkFF1,clkFF2,clkFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI
+ signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI
+
+ signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal counter : integer := 31; -- counter for data position
+
+ constant COUNTER_RESET_VALUE : integer := PPU_RAM_BUS_ADDR_WIDTH + PPU_RAM_BUS_DATA_WIDTH - 1;
begin
-
process (SYSCLK)
begin
- if rising_edge(SYSCLK) then
+ if RESET = '1' then
+ counter <= COUNTER_RESET_VALUE;
+ DATA <= (others => '0');
+ elsif rising_edge(SYSCLK) then
-- flip flop for clk SPI to synchronise a
- PulseFF0 <= SPI_CLK;
- PulseFF1 <= PulseFF0;
- PulseFF2 <= PulseFF1;
- PulseFF3 <= PulseFF2;
- -- flip flop for data SPI to synchronise
+ clkFF0 <= SPI_CLK;
+ clkFF1 <= clkFF0;
+ clkFF2 <= clkFF1;
+ clkFF3 <= clkFF2;
+ -- flip flop for data SPI to synchronise
dataFF0 <= SPI_MOSI;
dataFF1 <= dataFF0;
dataFF2 <= dataFF1;
- dataFF3 <= dataFF2;
- -- flip flop for slave select SPI to synchronise
- ssFF0 <= SPI_CS;
- ssFF1 <= ssFF0;
- ssFF2 <= ssFF1;
- ssFF3 <= ssFF2;
- -- check if slave select signal has falling edge (slave is selected by master)
- if(ssFF3 = '1' and ssFF2 = '0') then
- -- reset counter if true
- counter <= 23;
- -- disable data read if rising edge (slave is not selected)
- elsif (ssFF3 = '0' and ssFF2 = '1') then
- enable <= '0';
- end if;
- -- check if synchronised slave select signal is falling edge or data read is enabled
- if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then
- enable <= '1'; -- enable data read
- if (PulseFF3 = '0' and PulseFF2 = '1') then -- check for rising edge of clk SPI
- if counter > -1 then
- counter <= counter - 1;
- -- data transfer into vector
- SPI_REG(counter) <= dataFF3;
- end if;
+ dataFF3 <= dataFF2;
+
+ if (clkFF3 = '0' and clkFF2 = '1') then -- check for rising edge of clk SPI
+ if counter > -1 then
+ counter <= counter - 1;
+ -- data transfer into vector
+ SPI_REG(counter) <= dataFF3;
end if;
- -- check if counter is done
- if counter = -1 then
- counter <= 23; -- reset counter
- DATA <= SPI_REG;
- end if;
- elsif (enable = '0') then
- -- DATA <= SPI_REG;
+ end if;
+ -- check if counter is done
+ if counter = -1 then
+ counter <= COUNTER_RESET_VALUE; -- reset counter
+ DATA <= SPI_REG;
end if;
end if;
end process;
diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd
new file mode 100644
index 0000000..a8aa8c2
--- /dev/null
+++ b/basys3/basys3.srcs/spi_tb.vhd
@@ -0,0 +1,259 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+use work.ppu_consts.all;
+
+entity spi_tb is
+end spi_tb;
+
+architecture behavioral of spi_tb is
+ signal SYSCLK : std_logic := '0';
+ signal SPI_CLK : std_logic := '0';
+ signal SPI_MOSI : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
+begin
+ uut : entity work.spi port map(
+ SYSCLK => SYSCLK,
+ RESET => RESET,
+ DATA => DATA,
+ SPI_CLK => SPI_CLK,
+ SPI_MOSI => SPI_MOSI);
+
+ sysclkgen: process
+ begin
+ for i in 0 to 10000 loop
+ wait for 5 ns;
+ SYSCLK <= '1';
+ wait for 5 ns;
+ SYSCLK <= '0';
+ end loop;
+ wait; -- stop for simulator
+ end process;
+
+ spi_data: process
+ begin
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ SPI_MOSI <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ wait for 50 ns;
+ SPI_CLK <= '1';
+ wait for 50 ns;
+ SPI_CLK <= '0';
+ wait for 50 ns;
+ RESET <= '1';
+ wait for 50 ns;
+ RESET <= '0';
+
+
+ wait; -- stop for simulator
+ end process;
+end;
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd
index 0354b62..84ab7eb 100644
--- a/basys3/basys3.srcs/top.vhd
+++ b/basys3/basys3.srcs/top.vhd
@@ -8,7 +8,6 @@ entity top is port (
RESET : in std_logic; -- global (async) system reset
SPI_CLK : in std_logic; -- incoming clock of SPI
SPI_MOSI : in std_logic; -- incoming data of SPI
- SPI_CS : in std_logic; -- incoming select of SPI
WEN : in std_logic; -- PPU VRAM write enable
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
VSYNC, HSYNC : out std_logic; -- VGA sync out
@@ -30,7 +29,7 @@ architecture Behavioral of top is
SYSCLK : in std_logic; -- clock basys3 100MHz
SPI_CLK : in std_logic; -- incoming clock of SPI
SPI_MOSI : in std_logic; -- incoming data of SPI
- SPI_CS : in std_logic; -- incoming select of SPI
+ RESET : in std_logic; -- async reset
DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read
end component;
@@ -40,9 +39,9 @@ architecture Behavioral of top is
begin
serial_peripheral_interface: component spi port map(
SYSCLK => SYSCLK,
+ RESET => RESET,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
- SPI_CS => '1',
DATA => SPI_DATA);
picture_processing_unit: component ppu port map(