diff options
Diffstat (limited to 'basys3/basys3.srcs')
| -rw-r--r-- | basys3/basys3.srcs/io.xdc | 3 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu.vhd | 5 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl.vhd | 2 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg.vhd | 3 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg_consts.vhd | 3 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_sprite_bg.vhd | 1 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_sprite_fg.vhd | 21 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_tb.vhd.m4 | 5 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci | 12 | ||||
| -rw-r--r-- | basys3/basys3.srcs/spi.vhd | 5 | ||||
| -rw-r--r-- | basys3/basys3.srcs/spi_tb.vhd | 967 | ||||
| -rw-r--r-- | basys3/basys3.srcs/spi_tb.vhd.m4 | 1 |
12 files changed, 1006 insertions, 22 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc index cda8030..2f17073 100644 --- a/basys3/basys3.srcs/io.xdc +++ b/basys3/basys3.srcs/io.xdc @@ -91,3 +91,6 @@ set_property PACKAGE_PIN U19 [get_ports {DBG_LEDS_OUT[2]}] set_property PACKAGE_PIN E19 [get_ports {DBG_LEDS_OUT[1]}] set_property PACKAGE_PIN U16 [get_ports {DBG_LEDS_OUT[0]}] + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd index 445ae14..e6f959d 100644 --- a/basys3/basys3.srcs/ppu.vhd +++ b/basys3/basys3.srcs/ppu.vhd @@ -23,6 +23,7 @@ architecture Behavioral of ppu is RESET : in std_logic; -- async reset SPRITE_BG : out ppu_sprite_bg_pl_state := PL_BG_IDLE; -- sprite info fetch + sprite pixel fetch SPRITE_FG : out ppu_sprite_fg_pl_state := PL_FG_IDLE; -- sprite pixel fetch + SPRITE_FG_HIT : out ppu_sprite_fg_hit_pl_state := PL_HIT_INACCURATE; -- foreground hit accuracy DONE : out std_logic; -- last pipeline stage done READY : out std_logic); -- rgb buffer propagation ready end component; @@ -109,6 +110,7 @@ architecture Behavioral of ppu is CLK : in std_logic; -- system clock RESET : in std_logic; -- reset internal memory and clock counters PL_STAGE : in ppu_sprite_fg_pl_state; -- pipeline stage + PL_HIT : in ppu_sprite_fg_hit_pl_state; OE : in std_logic; -- output enable (of CIDX) X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y @@ -166,6 +168,7 @@ architecture Behavioral of ppu is signal PL_DONE, PL_READY : std_logic; -- pipeline stages signal PL_SPRITE_BG : ppu_sprite_bg_pl_state; signal PL_SPRITE_FG : ppu_sprite_fg_pl_state; + signal PL_SPRITE_FG_HIT : ppu_sprite_fg_hit_pl_state; signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic; signal TMM_W_ADDR, TMM_R_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); -- read/write TMM addr (dual port) signal BAM_W_ADDR, BAM_R_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); -- read/write BAM addr (dual port) @@ -202,6 +205,7 @@ begin RESET => PCEG_RESET, SPRITE_FG => PL_SPRITE_FG, SPRITE_BG => PL_SPRITE_BG, + SPRITE_FG_HIT => PL_SPRITE_FG_HIT, DONE => PL_DONE, READY => PL_READY); @@ -289,6 +293,7 @@ begin CLK => SYSCLK, RESET => SYSRST, PL_STAGE => PL_SPRITE_FG, + PL_HIT => PL_SPRITE_FG_HIT, OE => FG_EN(FG_IDX), X => X, Y => Y, diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd index ce53557..ac8fbcf 100644 --- a/basys3/basys3.srcs/ppu_dispctl.vhd +++ b/basys3/basys3.srcs/ppu_dispctl.vhd @@ -129,7 +129,7 @@ begin if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE + PPU_VGA_H_SYNC then TMP_NHSYNC := '0'; end if; end if; - if falling_edge(TPIXCLK) then -- NOTE: falling edge used because of clock offset of 90 (should be 270) + if rising_edge(TPIXCLK) then T_POS_X <= TMP_T_POS_X; if TMP_NACTIVE = '1' then diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd index 67b7e1c..e3c16e8 100644 --- a/basys3/basys3.srcs/ppu_pceg.vhd +++ b/basys3/basys3.srcs/ppu_pceg.vhd @@ -8,6 +8,7 @@ entity ppu_pceg is port( RESET : in std_logic; -- async reset SPRITE_BG : out ppu_sprite_bg_pl_state := PL_BG_IDLE; -- sprite info fetch + sprite pixel fetch SPRITE_FG : out ppu_sprite_fg_pl_state := PL_FG_IDLE; -- sprite pixel fetch + SPRITE_FG_HIT : out ppu_sprite_fg_hit_pl_state := PL_HIT_INACCURATE; -- foreground hit accuracy DONE : out std_logic; -- last pipeline stage done READY : out std_logic); -- rgb buffer propagation ready end ppu_pceg; @@ -32,6 +33,7 @@ begin READY <= '0'; SPRITE_BG <= PL_BG_IDLE; SPRITE_FG <= PL_FG_IDLE; + SPRITE_FG_HIT <= PL_HIT_INACCURATE; when 1 => SPRITE_BG <= PL_BG_BAM_ADDR; SPRITE_FG <= PL_FG_TMM_ADDR; @@ -44,6 +46,7 @@ begin when 5 => SPRITE_BG <= PL_BG_TMM_ADDR; SPRITE_FG <= PL_FG_IDLE; + SPRITE_FG_HIT <= PL_HIT_ACCURATE; when 6 => null; when 7 => SPRITE_BG <= PL_BG_IDLE; diff --git a/basys3/basys3.srcs/ppu_pceg_consts.vhd b/basys3/basys3.srcs/ppu_pceg_consts.vhd index eac4d23..3a9775a 100644 --- a/basys3/basys3.srcs/ppu_pceg_consts.vhd +++ b/basys3/basys3.srcs/ppu_pceg_consts.vhd @@ -14,5 +14,8 @@ package ppu_pceg_consts is PL_FG_IDLE, PL_FG_TMM_ADDR, PL_FG_TMM_DATA); + type ppu_sprite_fg_hit_pl_state is ( + PL_HIT_INACCURATE, + PL_HIT_ACCURATE); end package ppu_pceg_consts; diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd index cc9c24b..ef8ffc8 100644 --- a/basys3/basys3.srcs/ppu_sprite_bg.vhd +++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd @@ -7,7 +7,6 @@ use ieee.numeric_std.all; use work.ppu_consts.all; use work.ppu_pceg_consts.all; --- TODO: add input stable / output stable pipeline stages if this doesn't work with propagation delays entity ppu_sprite_bg is port( -- inputs CLK : in std_logic; -- system clock diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd index 89e6e66..d6ffe16 100644 --- a/basys3/basys3.srcs/ppu_sprite_fg.vhd +++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd @@ -1,13 +1,10 @@ library ieee; -library work; - use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.ppu_consts.all; use work.ppu_pceg_consts.all; --- TODO: add input stable / output stable pipeline stages if this doesn't work with propagation delays entity ppu_sprite_fg is -- foreground sprite generic ( IDX : natural := 0); -- sprite index number @@ -16,6 +13,7 @@ entity ppu_sprite_fg is -- foreground sprite CLK : in std_logic; -- system clock RESET : in std_logic; -- reset internal memory and clock counters PL_STAGE : in ppu_sprite_fg_pl_state; -- pipeline stage + PL_HIT : in ppu_sprite_fg_hit_pl_state; OE : in std_logic; -- output enable (of CIDX) X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y @@ -72,7 +70,7 @@ architecture Behavioral of ppu_sprite_fg is alias FAM_REG_FLIP_V is INT_FAM(30); -- Flip vertically alias FAM_REG_POS_H is INT_FAM(29 downto 21); -- horizontal position (offset by -16) alias FAM_REG_POS_V is INT_FAM(20 downto 13); -- vertical position (offset by -16) - alias FAM_REG_COL_IDX is INT_FAM(12 downto 10); -- Palette index for tile + alias FAM_REG_PAL_IDX is INT_FAM(12 downto 10); -- Palette index for tile alias FAM_REG_TILE_IDX is INT_FAM(9 downto 0); -- Tilemap index signal SPRITE_ACTIVE : std_logic := '0'; -- is pixel in bounding box of sprite @@ -83,7 +81,7 @@ architecture Behavioral of ppu_sprite_fg is signal TRANS_TILE_PIDX : integer := 0; -- index of pixel within tile (reading order) signal TILEMAP_WORD : unsigned(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM - signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette + signal TMM_DATA_COL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette begin -- FAM memory @@ -102,7 +100,7 @@ begin REG => INT_FAM); -- CIDX combination - T_CIDX <= FAM_REG_COL_IDX & TMM_DATA_PAL_IDX; + T_CIDX <= FAM_REG_PAL_IDX & TMM_DATA_COL_IDX; -- output drivers CIDX <= T_CIDX when OE = '1' else (others => 'Z'); -- TMM memory @@ -136,14 +134,15 @@ begin inaccurate_occlusion_shims: if IDX >= PPU_ACCURATE_FG_SPRITE_COUNT generate -- state machine for synchronizing pipeline stages begin - HIT <= SPRITE_ACTIVE; + HIT <= (SPRITE_ACTIVE) when PL_HIT = PL_HIT_INACCURATE else + (SPRITE_ACTIVE and (or TMM_DATA_COL_IDX)) when PL_HIT = PL_HIT_ACCURATE else '0'; -- only fetch if OE is high, and during the second pipeline stage TMM_ADDR <= R_TMM_ADDR when OE = '1' and PL_STAGE = PL_FG_TMM_ADDR else (others => 'Z'); T_TMM_ADDR <= std_logic_vector(TILEMAP_WORD + to_unsigned(TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address -- TMM DATA with PIXEL_BIT_OFFSET select - TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0, + TMM_DATA_COL_IDX <= R_TMM_DATA(2 downto 0) when 0, R_TMM_DATA(5 downto 3) when 1, R_TMM_DATA(8 downto 6) when 2, R_TMM_DATA(11 downto 9) when 3, @@ -156,6 +155,8 @@ begin -- reset internal pipeline registers R_TMM_ADDR <= (others => '0'); R_TMM_DATA <= (others => '0'); + elsif OE = '0' then + null; -- don't read/write if current sprite is not the top sprite elsif rising_edge(CLK) then case PL_STAGE is when PL_FG_TMM_ADDR => @@ -175,10 +176,10 @@ begin signal TMM_CACHE_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal TMM_CACHE : std_logic_vector((PPU_SPRITE_WORD_COUNT * PPU_TMM_DATA_WIDTH)-1 downto 0); begin - HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX); + HIT <= SPRITE_ACTIVE and (or TMM_DATA_COL_IDX); -- palette color at pixel - TMM_DATA_PAL_IDX <= TMM_CACHE(TRANS_TILE_PIDX * integer(PPU_PALETTE_COLOR_WIDTH) + integer(PPU_PALETTE_COLOR_WIDTH)-1 downto TRANS_TILE_PIDX * integer(PPU_PALETTE_COLOR_WIDTH)); + TMM_DATA_COL_IDX <= TMM_CACHE(TRANS_TILE_PIDX * integer(PPU_PALETTE_COLOR_WIDTH) + integer(PPU_PALETTE_COLOR_WIDTH)-1 downto TRANS_TILE_PIDX * integer(PPU_PALETTE_COLOR_WIDTH)); TMM_ADDR <= T_TMM_ADDR when TMM_CACHE_UPDATE_TURN else (others => 'Z'); diff --git a/basys3/basys3.srcs/ppu_tb.vhd.m4 b/basys3/basys3.srcs/ppu_tb.vhd.m4 index 97f0aef..8e405a9 100644 --- a/basys3/basys3.srcs/ppu_tb.vhd.m4 +++ b/basys3/basys3.srcs/ppu_tb.vhd.m4 @@ -49,7 +49,10 @@ begin process begin - -- undivert(`test-image-ppu.tb.vhd') -- m4 macro expansion (see makefile) + RESET <= '1'; + wait for 50 ns; + RESET <= '0'; + -- undivert(`test-foreground-sprite-ppu.tb.vhd') -- m4 macro expansion (see makefile) wait; -- stop after one loop (process loops in simulator) end process; end Behavioral; diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci index 064d3ff..97aad5e 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci @@ -88,7 +88,7 @@ "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "6.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_PHASE": [ { "value": "90.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -173,7 +173,7 @@ "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLKOUT1_DIVIDE": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT1_PHASE": [ { "value": "90.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -339,7 +339,7 @@ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW1": [ { "value": "__npxclk__25.00000______0.000______50.0______191.696____114.212", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "__tpxclk___6.25000_____90.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "__tpxclk___6.25000______0.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], @@ -353,7 +353,7 @@ "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -374,7 +374,7 @@ "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -424,7 +424,7 @@ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd index 6ca2828..ba96eee 100644 --- a/basys3/basys3.srcs/spi.vhd +++ b/basys3/basys3.srcs/spi.vhd @@ -22,7 +22,7 @@ architecture Behavioral of spi is constant COUNTER_RESET_VALUE : integer := PPU_RAM_BUS_ADDR_WIDTH + PPU_RAM_BUS_DATA_WIDTH - 1; begin process (SYSCLK) - variable i : integer range 0 to COUNTER_RESET_VALUE := COUNTER_RESET_VALUE; -- counter for data position + variable i : integer range 0 to COUNTER_RESET_VALUE := COUNTER_RESET_VALUE; -- received bits counter variable data_r : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '1'); -- data register begin if RESET = '1' then @@ -53,7 +53,8 @@ begin srFF2 <= srFF1; if (clkFF3 = '0' and clkFF2 = '1') then - data_r(i) := dataFF2; + -- data_r(i) := dataFF2; + data_r := data_r(data_r'high-1 downto data_r'low) & dataFF2; if i = 0 then i := COUNTER_RESET_VALUE; diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd index fea96b9..c9c320e 100644 --- a/basys3/basys3.srcs/spi_tb.vhd +++ b/basys3/basys3.srcs/spi_tb.vhd @@ -38,7 +38,7 @@ begin process begin - -- -- 0xdc00: 0f0f + -- -- 0xdc00: 0000 SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; @@ -159,6 +159,247 @@ SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +-- 0xffff: ffff +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; +-- +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; @@ -183,12 +424,43 @@ SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; +-- 0xdc00: 0808 +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; @@ -207,6 +479,699 @@ SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; +-- +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +-- 0xffff: ffff +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; +-- +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +-- 0xdc00: 0f0f +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; +-- +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '0'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +-- 0xffff: ffff +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; +-- +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + +SPI_DATA <= '1'; +wait for 50 ns; +SPI_CLK <= '1'; +wait for 50 ns; +SPI_CLK <= '0'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; diff --git a/basys3/basys3.srcs/spi_tb.vhd.m4 b/basys3/basys3.srcs/spi_tb.vhd.m4 index cf76b2c..00bf088 100644 --- a/basys3/basys3.srcs/spi_tb.vhd.m4 +++ b/basys3/basys3.srcs/spi_tb.vhd.m4 @@ -21,6 +21,7 @@ begin RESET => RESET, DO => open, DI => SPI_DATA, + SR => '0', DCK => SPI_CLK, WEN => open); |