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-rw-r--r--basys3/basys3.srcs/io.xdc33
-rw-r--r--basys3/basys3.srcs/ppu.vhd26
-rw-r--r--basys3/basys3.srcs/ppu_aux.vhd4
-rw-r--r--basys3/basys3.srcs/top.vhd21
4 files changed, 59 insertions, 25 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc
index 218d2f1..cda8030 100644
--- a/basys3/basys3.srcs/io.xdc
+++ b/basys3/basys3.srcs/io.xdc
@@ -1,16 +1,32 @@
set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
-set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
+set_property PACKAGE_PIN L2 [get_ports SPI_MOSI]
set_property PACKAGE_PIN J2 [get_ports SPI_CLK]
-set_property PACKAGE_PIN L2 [get_ports SPI_MOSI]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
+
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_SR]
+set_property PACKAGE_PIN H1 [get_ports SPI_SR]
+set_property PULLDOWN true [get_ports SPI_SR]
+
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports HBLANK]
+set_property PACKAGE_PIN K2 [get_ports HBLANK]
+
+set_property IOSTANDARD LVCMOS33 [get_ports VBLANK]
+set_property PACKAGE_PIN J1 [get_ports VBLANK]
+
+
set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]
+set_property PACKAGE_PIN W5 [get_ports SYSCLK]
+
set_property IOSTANDARD LVCMOS33 [get_ports RESET]
+set_property PACKAGE_PIN T18 [get_ports RESET]
+
set_property IOSTANDARD LVCMOS33 [get_ports HSYNC]
set_property IOSTANDARD LVCMOS33 [get_ports VSYNC]
-set_property PACKAGE_PIN W5 [get_ports SYSCLK]
-set_property PACKAGE_PIN T18 [get_ports RESET]
set_property PACKAGE_PIN P19 [get_ports HSYNC]
set_property PACKAGE_PIN R19 [get_ports VSYNC]
@@ -40,14 +56,6 @@ set_property PACKAGE_PIN K18 [get_ports {B[2]}]
set_property PACKAGE_PIN L18 [get_ports {B[1]}]
set_property PACKAGE_PIN N18 [get_ports {B[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports VBLANK]
-set_property IOSTANDARD LVCMOS33 [get_ports SPI_RESET]
-
-set_property PACKAGE_PIN C16 [get_ports VBLANK]
-set_property PACKAGE_PIN J1 [get_ports SPI_RESET]
-
-
-
set_property IOSTANDARD LVCMOS33 [get_ports DBG_DISP_ADDR]
set_property PACKAGE_PIN R2 [get_ports DBG_DISP_ADDR]
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[15]}]
@@ -83,4 +91,3 @@ set_property PACKAGE_PIN U19 [get_ports {DBG_LEDS_OUT[2]}]
set_property PACKAGE_PIN E19 [get_ports {DBG_LEDS_OUT[1]}]
set_property PACKAGE_PIN U16 [get_ports {DBG_LEDS_OUT[0]}]
-set_property PULLDOWN true [get_ports SPI_RESET]
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index c6864df..445ae14 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -13,7 +13,8 @@ entity ppu is port(
DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
VSYNC, HSYNC : out std_logic; -- VGA sync out
- VBLANK : out std_logic); -- vblank for synchronization
+ VBLANK, HBLANK : out std_logic; -- vblank and hblank for synchronization
+ RESOUT : out std_logic); -- reset out
end ppu;
architecture Behavioral of ppu is
@@ -75,7 +76,8 @@ architecture Behavioral of ppu is
-- aux outputs
BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
- FG_FETCH : out std_logic);
+ FG_FETCH : out std_logic;
+ RESOUT : out std_logic);
end component;
component ppu_sprite_bg port( -- background sprite
-- inputs
@@ -180,10 +182,10 @@ architecture Behavioral of ppu is
signal UR,UG,UB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- palette lookup output RGB
signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
- signal FG_FETCH : std_logic;
signal NVSYNC, NHSYNC, THBLANK, TVBLANK : std_logic;
signal ACTIVE : std_logic;
signal PCEG_RESET : std_logic;
+ signal FG_FETCH, FG_FETCH_S, FG_FETCH_R : std_logic := '0';
begin
SYSCLK <= CLK100;
SYSRST <= RESET;
@@ -193,6 +195,7 @@ begin
PCEG_RESET <= SYSRST or (not ACTIVE);
VBLANK <= TVBLANK;
+ HBLANK <= THBLANK;
pipeline_clock_edge_generator : component ppu_pceg port map(
CLK => SYSCLK,
@@ -247,7 +250,22 @@ begin
AUX_DATA => DATA(PPU_AUX_DATA_WIDTH-1 downto 0),
BG_SHIFT_X => BG_SHIFT_X,
BG_SHIFT_Y => BG_SHIFT_Y,
- FG_FETCH => FG_FETCH);
+ FG_FETCH => FG_FETCH_S,
+ RESOUT => RESOUT);
+
+ -- set/reset TODO: reset on scanline 1 (buffer VBLANK to check edge)
+ process(SYSCLK)
+ begin
+ if SYSRST = '1' then
+ FG_FETCH <= '0';
+ elsif rising_edge(SYSCLK) then
+ if FG_FETCH_S = '1' then
+ FG_FETCH <= '1';
+ elsif FG_FETCH_R = '1' then
+ FG_FETCH <= '0';
+ end if;
+ end if;
+ end process;
background_sprite : component ppu_sprite_bg port map(
CLK => SYSCLK,
diff --git a/basys3/basys3.srcs/ppu_aux.vhd b/basys3/basys3.srcs/ppu_aux.vhd
index 9062bc4..199fb76 100644
--- a/basys3/basys3.srcs/ppu_aux.vhd
+++ b/basys3/basys3.srcs/ppu_aux.vhd
@@ -16,7 +16,8 @@ entity ppu_aux is port(
-- aux outputs
BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
- FG_FETCH : out std_logic);
+ FG_FETCH : out std_logic;
+ RESOUT : out std_logic);
end ppu_aux;
architecture Behavioral of ppu_aux is
@@ -38,6 +39,7 @@ architecture Behavioral of ppu_aux is
signal INT_REG : std_logic_vector(2 * PPU_AUX_DATA_WIDTH - 1 downto 0);
begin
-- docs/architecture.md#auxiliary-memory
+ RESOUT <= INT_REG(18);
FG_FETCH <= INT_REG(17);
BG_SHIFT_X <= INT_REG(16 downto 8);
BG_SHIFT_Y <= INT_REG(7 downto 0);
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd
index e69c622..cc98821 100644
--- a/basys3/basys3.srcs/top.vhd
+++ b/basys3/basys3.srcs/top.vhd
@@ -8,12 +8,12 @@ entity top is port (
RESET : in std_logic; -- global (async) system reset
SPI_CLK : in std_logic; -- incoming clock of SPI
SPI_MOSI : in std_logic; -- incoming data of SPI
- SPI_RESET : in std_logic; -- PPU VRAM write enable
+ SPI_SR : in std_logic; -- PPU VRAM write enable
DBG_DISP_ADDR : in std_logic; -- display address/data switch (debug)
DBG_LEDS_OUT : out std_logic_vector(15 downto 0); -- debug address/data output leds
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
VSYNC, HSYNC : out std_logic; -- VGA sync out
- VBLANK : out std_logic); -- vblank for synchronization
+ VBLANK, HBLANK : out std_logic); -- vblank for synchronization
end top;
architecture Behavioral of top is
@@ -25,7 +25,8 @@ architecture Behavioral of top is
DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
VSYNC, HSYNC : out std_logic; -- VGA sync out
- VBLANK : out std_logic); -- vblank for synchronization
+ VBLANK, HBLANK : out std_logic; -- vblank and hblank for synchronization
+ RESOUT : out std_logic); -- reset out
end component;
component spi port (
SYSCLK : in std_logic; -- system clock (100MHz)
@@ -37,17 +38,21 @@ architecture Behavioral of top is
WEN : out std_logic := '0'); -- write enable (triggers during each word to propagate previous word)
end component;
+ signal SYSRST : std_logic := '0'; -- system reset
+ signal PPU_RST_OUT : std_logic; -- ppu reset out
signal PPU_WEN : std_logic;
signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
alias SPI_DATA_ADDR is SPI_DATA(31 downto 16);
alias SPI_DATA_DATA is SPI_DATA(15 downto 0);
begin
+ SYSRST <= RESET or PPU_RST_OUT;
+
serial_peripheral_interface: component spi port map(
SYSCLK => SYSCLK,
- RESET => RESET,
+ RESET => SYSRST,
DCK => SPI_CLK,
DI => SPI_MOSI,
- SR => SPI_RESET,
+ SR => SPI_SR,
DO => SPI_DATA,
WEN => PPU_WEN);
@@ -55,7 +60,7 @@ begin
picture_processing_unit: component ppu port map(
CLK100 => SYSCLK,
- RESET => RESET,
+ RESET => SYSRST,
WEN => PPU_WEN,
ADDR => SPI_DATA_ADDR,
DATA => SPI_DATA_DATA,
@@ -64,5 +69,7 @@ begin
B => B,
VSYNC => VSYNC,
HSYNC => HSYNC,
- VBLANK => VBLANK);
+ VBLANK => VBLANK,
+ HBLANK => HBLANK,
+ RESOUT => PPU_RST_OUT);
end Behavioral;