diff options
Diffstat (limited to 'basys3/basys3.srcs')
| -rw-r--r-- | basys3/basys3.srcs/ppu.vhd | 32 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl.vhd | 14 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg.vhd | 29 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_sprite_bg.vhd | 2 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_sprite_fg.vhd | 23 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci | 36 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci | 32 | ||||
| -rw-r--r-- | basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci | 32 | ||||
| -rw-r--r-- | basys3/basys3.srcs/top.vhd | 3 |
9 files changed, 89 insertions, 114 deletions
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd index e6f959d..3f92a7e 100644 --- a/basys3/basys3.srcs/ppu.vhd +++ b/basys3/basys3.srcs/ppu.vhd @@ -24,8 +24,7 @@ architecture Behavioral of ppu is SPRITE_BG : out ppu_sprite_bg_pl_state := PL_BG_IDLE; -- sprite info fetch + sprite pixel fetch SPRITE_FG : out ppu_sprite_fg_pl_state := PL_FG_IDLE; -- sprite pixel fetch SPRITE_FG_HIT : out ppu_sprite_fg_hit_pl_state := PL_HIT_INACCURATE; -- foreground hit accuracy - DONE : out std_logic; -- last pipeline stage done - READY : out std_logic); -- rgb buffer propagation ready + DISPCTL_BWEN : out std_logic := '0'); -- display controller scanline buffer write enable end component; component ppu_addr_dec port( -- address decoder WEN : in std_logic; -- EXT write enable @@ -47,11 +46,8 @@ architecture Behavioral of ppu is addra : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); dina : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); clkb : in std_logic; - rstb : in std_logic; addrb : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - doutb : out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); - rsta_busy : out std_logic; - rstb_busy : out std_logic); + doutb : out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0)); end component; component ppu_tmm port( -- TMM block memory clka : in std_logic; @@ -59,11 +55,8 @@ architecture Behavioral of ppu is addra : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); dina : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); clkb : in std_logic; - rstb : in std_logic; addrb : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - doutb : out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); - rsta_busy : out std_logic; - rstb_busy : out std_logic); + doutb : out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0)); end component; component ppu_aux port( CLK : in std_logic; -- system clock @@ -155,7 +148,7 @@ architecture Behavioral of ppu is X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in - PREADY : in std_logic; -- current pixel ready (pixel color is stable) + BWEN : in std_logic; -- scanline buffer write enable RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out NVSYNC, NHSYNC : out std_logic; -- VGA sync out @@ -165,10 +158,10 @@ architecture Behavioral of ppu is -- signals signal SYSCLK, SYSRST : std_logic; -- system clock and reset - signal PL_DONE, PL_READY : std_logic; -- pipeline stages signal PL_SPRITE_BG : ppu_sprite_bg_pl_state; signal PL_SPRITE_FG : ppu_sprite_fg_pl_state; signal PL_SPRITE_FG_HIT : ppu_sprite_fg_hit_pl_state; + signal PL_DISPCTL_BWEN : std_logic; signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic; signal TMM_W_ADDR, TMM_R_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); -- read/write TMM addr (dual port) signal BAM_W_ADDR, BAM_R_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); -- read/write BAM addr (dual port) @@ -206,8 +199,7 @@ begin SPRITE_FG => PL_SPRITE_FG, SPRITE_BG => PL_SPRITE_BG, SPRITE_FG_HIT => PL_SPRITE_FG_HIT, - DONE => PL_DONE, - READY => PL_READY); + DISPCTL_BWEN => PL_DISPCTL_BWEN); address_decoder : component ppu_addr_dec port map( WEN => WEN, @@ -229,22 +221,16 @@ begin addra => BAM_W_ADDR, dina => DATA(PPU_BAM_DATA_WIDTH-1 downto 0), clkb => SYSCLK, - rstb => SYSRST, addrb => BAM_R_ADDR, - doutb => BAM_R_DATA, - rsta_busy => open, - rstb_busy => open); + doutb => BAM_R_DATA); tilemap_memory : component ppu_tmm port map( clka => SYSCLK, wea => (others => TMM_WEN), addra => TMM_W_ADDR, dina => DATA(PPU_TMM_DATA_WIDTH-1 downto 0), clkb => SYSCLK, - rstb => SYSRST, addrb => TMM_R_ADDR, - doutb => TMM_R_DATA, - rsta_busy => open, - rstb_busy => open); + doutb => TMM_R_DATA); aux : component ppu_aux port map( CLK => SYSCLK, @@ -328,7 +314,7 @@ begin display_controller : component ppu_dispctl port map( SYSCLK => SYSCLK, RESET => SYSRST, - PREADY => PL_READY, + BWEN => PL_DISPCTL_BWEN, X => X, Y => Y, RI => UR, diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd index ac8fbcf..1bff09d 100644 --- a/basys3/basys3.srcs/ppu_dispctl.vhd +++ b/basys3/basys3.srcs/ppu_dispctl.vhd @@ -11,7 +11,7 @@ entity ppu_dispctl is port( X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in - PREADY : in std_logic; -- current pixel ready (pixel color is stable) + BWEN : in std_logic; -- scanline buffer write enable RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out NVSYNC, NHSYNC : out std_logic; -- VGA sync out @@ -32,11 +32,8 @@ architecture Behavioral of ppu_dispctl is addra : in std_logic_vector(PPU_DISPCTL_SLBUF_ADDR_WIDTH-1 downto 0); dina : in std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0); clkb : in std_logic; - rstb : in std_logic; addrb : in std_logic_vector(PPU_DISPCTL_SLBUF_ADDR_WIDTH-1 downto 0); - doutb : out std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0); - rsta_busy : out std_logic; - rstb_busy : out std_logic); + doutb : out std_logic_vector(PPU_RGB_COLOR_OUTPUT_DEPTH-1 downto 0)); end component; signal NPIXCLK, TPIXCLK : std_logic; signal NHCOUNT, NVCOUNT : unsigned(PPU_VGA_SIGNAL_PIXEL_WIDTH-1 downto 0) := (others => '0'); @@ -144,15 +141,12 @@ begin scanline_buffer : component ppu_dispctl_slbuf port map( clka => SYSCLK, - wea => (others => PREADY), + wea => (others => BWEN), addra => ADDR_I, dina => DATA_I, clkb => SYSCLK, - rstb => RESET, addrb => ADDR_O, - doutb => DATA_O, - rsta_busy => open, - rstb_busy => open); + doutb => DATA_O); pixel_clock: component ppu_dispctl_pixclk port map( sysclk => SYSCLK, diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd index e3c16e8..f87c60d 100644 --- a/basys3/basys3.srcs/ppu_pceg.vhd +++ b/basys3/basys3.srcs/ppu_pceg.vhd @@ -9,8 +9,7 @@ entity ppu_pceg is port( SPRITE_BG : out ppu_sprite_bg_pl_state := PL_BG_IDLE; -- sprite info fetch + sprite pixel fetch SPRITE_FG : out ppu_sprite_fg_pl_state := PL_FG_IDLE; -- sprite pixel fetch SPRITE_FG_HIT : out ppu_sprite_fg_hit_pl_state := PL_HIT_INACCURATE; -- foreground hit accuracy - DONE : out std_logic; -- last pipeline stage done - READY : out std_logic); -- rgb buffer propagation ready + DISPCTL_BWEN : out std_logic := '0'); -- display controller scanline buffer write enable end ppu_pceg; architecture Behavioral of ppu_pceg is @@ -24,38 +23,32 @@ begin SPRITE_BG <= PL_BG_IDLE; SPRITE_FG <= PL_FG_IDLE; - DONE <= '0'; - READY <= '0'; + DISPCTL_BWEN <= '0'; elsif falling_edge(CLK) then case CLK_IDX is when 0 => - DONE <= '0'; - READY <= '0'; + DISPCTL_BWEN <= '0'; SPRITE_BG <= PL_BG_IDLE; SPRITE_FG <= PL_FG_IDLE; SPRITE_FG_HIT <= PL_HIT_INACCURATE; when 1 => SPRITE_BG <= PL_BG_BAM_ADDR; SPRITE_FG <= PL_FG_TMM_ADDR; - when 3 => - SPRITE_BG <= PL_BG_IDLE; - SPRITE_FG <= PL_FG_IDLE; - when 4 => + when 2 => SPRITE_BG <= PL_BG_BAM_DATA; SPRITE_FG <= PL_FG_TMM_DATA; - when 5 => + when 3 => SPRITE_BG <= PL_BG_TMM_ADDR; SPRITE_FG <= PL_FG_IDLE; SPRITE_FG_HIT <= PL_HIT_ACCURATE; - when 6 => null; - when 7 => - SPRITE_BG <= PL_BG_IDLE; - when 8 => - DONE <= '1'; + when 4 => SPRITE_BG <= PL_BG_TMM_DATA; - when 9 => + when 5 => SPRITE_BG <= PL_BG_IDLE; - READY <= '1'; + when 6 => + DISPCTL_BWEN <= '1'; + when 7 => + DISPCTL_BWEN <= '0'; when others => null; end case; diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd index ef8ffc8..9b6643e 100644 --- a/basys3/basys3.srcs/ppu_sprite_bg.vhd +++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd @@ -114,7 +114,7 @@ begin R_BAM_DATA <= (others => '0'); R_TMM_ADDR <= (others => '0'); R_TMM_DATA <= (others => '0'); - elsif rising_edge(CLK) then + elsif falling_edge(CLK) then BAM_ADDR_EN <= true when PL_STAGE = PL_BG_BAM_ADDR else false; TMM_ADDR_EN <= true when PL_STAGE = PL_BG_TMM_ADDR else false; -- R_BAM_ADDR <= T_BAM_ADDR; diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd index d6ffe16..9aabd88 100644 --- a/basys3/basys3.srcs/ppu_sprite_fg.vhd +++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd @@ -83,6 +83,9 @@ architecture Behavioral of ppu_sprite_fg is signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM signal TMM_DATA_COL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette + + signal PL_STAGE_NOW : ppu_sprite_fg_pl_state; + signal PL_HIT_NOW : ppu_sprite_fg_hit_pl_state; begin -- FAM memory FAM : component er_ram @@ -134,10 +137,10 @@ begin inaccurate_occlusion_shims: if IDX >= PPU_ACCURATE_FG_SPRITE_COUNT generate -- state machine for synchronizing pipeline stages begin - HIT <= (SPRITE_ACTIVE) when PL_HIT = PL_HIT_INACCURATE else - (SPRITE_ACTIVE and (or TMM_DATA_COL_IDX)) when PL_HIT = PL_HIT_ACCURATE else '0'; + HIT <= (SPRITE_ACTIVE) when PL_HIT_NOW = PL_HIT_INACCURATE else + (SPRITE_ACTIVE and (or TMM_DATA_COL_IDX)) when PL_HIT_NOW = PL_HIT_ACCURATE else '0'; -- only fetch if OE is high, and during the second pipeline stage - TMM_ADDR <= R_TMM_ADDR when OE = '1' and PL_STAGE = PL_FG_TMM_ADDR else (others => 'Z'); + TMM_ADDR <= R_TMM_ADDR when OE = '1' and PL_STAGE_NOW = PL_FG_TMM_ADDR else (others => 'Z'); T_TMM_ADDR <= std_logic_vector(TILEMAP_WORD + to_unsigned(TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address -- TMM DATA @@ -149,6 +152,16 @@ begin R_TMM_DATA(14 downto 12) when 4, (others => '0') when others; + -- rising edge clock process (buffer pipeline stage) + process(CLK, RESET) + begin + if rising_edge(CLK) then + PL_HIT_NOW <= PL_HIT; + PL_STAGE_NOW <= PL_STAGE; + end if; + end process; + + -- falling edge clock process (read buffered pipeline stage) process(CLK, RESET) begin if RESET = '1' then @@ -157,8 +170,8 @@ begin R_TMM_DATA <= (others => '0'); elsif OE = '0' then null; -- don't read/write if current sprite is not the top sprite - elsif rising_edge(CLK) then - case PL_STAGE is + elsif falling_edge(CLK) then + case PL_STAGE_NOW is when PL_FG_TMM_ADDR => R_TMM_ADDR <= T_TMM_ADDR; when PL_FG_TMM_DATA => diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci index c188e32..2241667 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci @@ -14,7 +14,7 @@ "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ], "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -44,24 +44,24 @@ "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Fill_Remaining_Memory_Locations": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "Use_RSTA_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ], - "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -76,7 +76,7 @@ "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], - "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] }, @@ -99,7 +99,7 @@ "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ], "C_INIT_FILE": [ { "value": "ppu_bam.mem", "resolve_type": "generated", "usage": "all" } ], - "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], @@ -115,7 +115,7 @@ "C_WRITE_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_READ_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRA_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], @@ -130,7 +130,7 @@ "C_READ_DEPTH_B": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -151,7 +151,7 @@ "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], @@ -190,11 +190,8 @@ "addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ], "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ], "clkb": [ { "direction": "in", "driver_value": "0" } ], - "rstb": [ { "direction": "in", "driver_value": "0" } ], "addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ], - "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "rsta_busy": [ { "direction": "out" } ], - "rstb_busy": [ { "direction": "out" } ] + "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ] }, "interfaces": { "CLK.ACLK": { @@ -255,8 +252,7 @@ "port_maps": { "ADDR": [ { "physical_name": "addrb" } ], "CLK": [ { "physical_name": "clkb" } ], - "DOUT": [ { "physical_name": "doutb" } ], - "RST": [ { "physical_name": "rstb" } ] + "DOUT": [ { "physical_name": "doutb" } ] } } }, diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci index 22b53c3..2a0ddf1 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci @@ -14,7 +14,7 @@ "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ], "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -44,24 +44,24 @@ "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Fill_Remaining_Memory_Locations": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ], - "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -76,7 +76,7 @@ "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], - "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] }, @@ -115,7 +115,7 @@ "C_WRITE_DEPTH_A": [ { "value": "640", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_READ_DEPTH_A": [ { "value": "640", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRA_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], @@ -130,7 +130,7 @@ "C_READ_DEPTH_B": [ { "value": "640", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRB_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -151,7 +151,7 @@ "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], @@ -190,11 +190,8 @@ "addra": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], "dina": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ], "clkb": [ { "direction": "in", "driver_value": "0" } ], - "rstb": [ { "direction": "in", "driver_value": "0" } ], "addrb": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], - "doutb": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], - "rsta_busy": [ { "direction": "out" } ], - "rstb_busy": [ { "direction": "out" } ] + "doutb": [ { "direction": "out", "size_left": "11", "size_right": "0" } ] }, "interfaces": { "CLK.ACLK": { @@ -255,8 +252,7 @@ "port_maps": { "ADDR": [ { "physical_name": "addrb" } ], "CLK": [ { "physical_name": "clkb" } ], - "DOUT": [ { "physical_name": "doutb" } ], - "RST": [ { "physical_name": "rstb" } ] + "DOUT": [ { "physical_name": "doutb" } ] } } }, diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci index e08ff96..1e10591 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci @@ -14,7 +14,7 @@ "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ], "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -44,9 +44,9 @@ "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Use_REGCEB_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -58,10 +58,10 @@ "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ], - "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "Use_RSTB_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Memory_Latch_B": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -76,7 +76,7 @@ "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ], "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ], "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], - "EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] }, @@ -115,7 +115,7 @@ "C_WRITE_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_READ_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], @@ -130,7 +130,7 @@ "C_READ_DEPTH_B": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -151,7 +151,7 @@ "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COUNT_36K_BRAM": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_18K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ], @@ -190,11 +190,8 @@ "addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ], "clkb": [ { "direction": "in", "driver_value": "0" } ], - "rstb": [ { "direction": "in", "driver_value": "0" } ], "addrb": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], - "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "rsta_busy": [ { "direction": "out" } ], - "rstb_busy": [ { "direction": "out" } ] + "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ] }, "interfaces": { "CLK.ACLK": { @@ -255,8 +252,7 @@ "port_maps": { "ADDR": [ { "physical_name": "addrb" } ], "CLK": [ { "physical_name": "clkb" } ], - "DOUT": [ { "physical_name": "doutb" } ], - "RST": [ { "physical_name": "rstb" } ] + "DOUT": [ { "physical_name": "doutb" } ] } } }, diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index cc98821..debd819 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -56,7 +56,8 @@ begin DO => SPI_DATA, WEN => PPU_WEN); - DBG_LEDS_OUT <= SPI_DATA_ADDR when DBG_DISP_ADDR = '1' else SPI_DATA_DATA; + -- DBG_LEDS_OUT <= SPI_DATA_ADDR when DBG_DISP_ADDR = '1' else SPI_DATA_DATA; + DBG_LEDS_OUT <= (others => '0'); picture_processing_unit: component ppu port map( CLK100 => SYSCLK, |