diff options
Diffstat (limited to 'basys3/basys3.srcs')
6 files changed, 58 insertions, 17 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc index fa1dbd0..3a8966a 100644 --- a/basys3/basys3.srcs/io.xdc +++ b/basys3/basys3.srcs/io.xdc @@ -1,6 +1,50 @@ -set_property PACKAGE_PIN A15 [get_ports SPI_CLK] -set_property PACKAGE_PIN C15 [get_ports SPI_CS] -set_property PACKAGE_PIN A17 [get_ports SPI_MOSI] set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI] set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS] set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK] + +set_property PACKAGE_PIN A15 [get_ports SPI_CLK] +set_property PACKAGE_PIN C15 [get_ports SPI_CS] +set_property PACKAGE_PIN A17 [get_ports SPI_MOSI] + +set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK] +set_property IOSTANDARD LVCMOS33 [get_ports RESET] +set_property IOSTANDARD LVCMOS33 [get_ports HSYNC] +set_property IOSTANDARD LVCMOS33 [get_ports VSYNC] + +set_property PACKAGE_PIN W5 [get_ports SYSCLK] +set_property PACKAGE_PIN T18 [get_ports RESET] +set_property PACKAGE_PIN P19 [get_ports HSYNC] +set_property PACKAGE_PIN R19 [get_ports VSYNC] + +set_property IOSTANDARD LVCMOS33 [get_ports {R[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {R[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {R[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {R[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {G[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {G[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {G[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {G[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}] + +set_property PACKAGE_PIN N19 [get_ports {R[3]}] +set_property PACKAGE_PIN J19 [get_ports {R[2]}] +set_property PACKAGE_PIN H19 [get_ports {R[1]}] +set_property PACKAGE_PIN G19 [get_ports {R[0]}] +set_property PACKAGE_PIN D17 [get_ports {G[3]}] +set_property PACKAGE_PIN G17 [get_ports {G[2]}] +set_property PACKAGE_PIN H17 [get_ports {G[1]}] +set_property PACKAGE_PIN J17 [get_ports {G[0]}] +set_property PACKAGE_PIN J18 [get_ports {B[3]}] +set_property PACKAGE_PIN K18 [get_ports {B[2]}] +set_property PACKAGE_PIN L18 [get_ports {B[1]}] +set_property PACKAGE_PIN N18 [get_ports {B[0]}] + +set_property IOSTANDARD LVCMOS33 [get_ports VBLANK] +set_property IOSTANDARD LVCMOS33 [get_ports WEN] + +set_property PACKAGE_PIN C16 [get_ports VBLANK] +set_property PACKAGE_PIN V13 [get_ports WEN] + diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci index 9f293d6..c188e32 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci @@ -163,7 +163,7 @@ "BOARD_CONNECTIONS": [ { "value": "" } ], "DEVICE": [ { "value": "xc7a35t" } ], "PACKAGE": [ { "value": "cpg236" } ], - "PREFHDL": [ { "value": "VHDL" } ], + "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-1" } ], diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci index 71185e4..620084f 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci @@ -588,7 +588,7 @@ "BOARD_CONNECTIONS": [ { "value": "" } ], "DEVICE": [ { "value": "xc7a35t" } ], "PACKAGE": [ { "value": "cpg236" } ], - "PREFHDL": [ { "value": "VHDL" } ], + "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-1" } ], diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci index 4677e6b..22b53c3 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci @@ -163,7 +163,7 @@ "BOARD_CONNECTIONS": [ { "value": "" } ], "DEVICE": [ { "value": "xc7a35t" } ], "PACKAGE": [ { "value": "cpg236" } ], - "PREFHDL": [ { "value": "VHDL" } ], + "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-1" } ], diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci index 958b9b9..e08ff96 100644 --- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci +++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci @@ -163,7 +163,7 @@ "BOARD_CONNECTIONS": [ { "value": "" } ], "DEVICE": [ { "value": "xc7a35t" } ], "PACKAGE": [ { "value": "cpg236" } ], - "PREFHDL": [ { "value": "VHDL" } ], + "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-1" } ], diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index 558489b..0354b62 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -11,21 +11,20 @@ entity top is port ( SPI_CS : in std_logic; -- incoming select of SPI WEN : in std_logic; -- PPU VRAM write enable R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); - NVSYNC, NHSYNC : out std_logic; -- native VGA out - TVBLANK, THBLANK : out std_logic); -- tiny VGA out + VSYNC, HSYNC : out std_logic; -- VGA sync out + VBLANK : out std_logic); -- vblank for synchronization end top; architecture Behavioral of top is component ppu port( CLK100 : in std_logic; -- system clock RESET : in std_logic; -- global (async) system reset - EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) WEN : in std_logic; -- PPU VRAM write enable ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); - NVSYNC, NHSYNC : out std_logic; -- native VGA out - TVBLANK, THBLANK : out std_logic); -- tiny VGA out + VSYNC, HSYNC : out std_logic; -- VGA sync out + VBLANK : out std_logic); -- vblank for synchronization end component; component spi port ( SYSCLK : in std_logic; -- clock basys3 100MHz @@ -49,15 +48,13 @@ begin picture_processing_unit: component ppu port map( CLK100 => SYSCLK, RESET => RESET, - EN => '1', WEN => WEN, ADDR => SPI_DATA_ADDR, DATA => SPI_DATA_DATA, R => R, G => G, B => B, - NVSYNC => NVSYNC, - NHSYNC => NHSYNC, - TVBLANK => TVBLANK, - THBLANK => THBLANK); + VSYNC => VSYNC, + HSYNC => HSYNC, + VBLANK => VBLANK); end Behavioral; |