diff options
Diffstat (limited to 'basys3/basys3.srcs/top.vhd')
| -rw-r--r-- | basys3/basys3.srcs/top.vhd | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index e69c622..cc98821 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -8,12 +8,12 @@ entity top is port ( RESET : in std_logic; -- global (async) system reset SPI_CLK : in std_logic; -- incoming clock of SPI SPI_MOSI : in std_logic; -- incoming data of SPI - SPI_RESET : in std_logic; -- PPU VRAM write enable + SPI_SR : in std_logic; -- PPU VRAM write enable DBG_DISP_ADDR : in std_logic; -- display address/data switch (debug) DBG_LEDS_OUT : out std_logic_vector(15 downto 0); -- debug address/data output leds R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); VSYNC, HSYNC : out std_logic; -- VGA sync out - VBLANK : out std_logic); -- vblank for synchronization + VBLANK, HBLANK : out std_logic); -- vblank for synchronization end top; architecture Behavioral of top is @@ -25,7 +25,8 @@ architecture Behavioral of top is DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); VSYNC, HSYNC : out std_logic; -- VGA sync out - VBLANK : out std_logic); -- vblank for synchronization + VBLANK, HBLANK : out std_logic; -- vblank and hblank for synchronization + RESOUT : out std_logic); -- reset out end component; component spi port ( SYSCLK : in std_logic; -- system clock (100MHz) @@ -37,17 +38,21 @@ architecture Behavioral of top is WEN : out std_logic := '0'); -- write enable (triggers during each word to propagate previous word) end component; + signal SYSRST : std_logic := '0'; -- system reset + signal PPU_RST_OUT : std_logic; -- ppu reset out signal PPU_WEN : std_logic; signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0); alias SPI_DATA_ADDR is SPI_DATA(31 downto 16); alias SPI_DATA_DATA is SPI_DATA(15 downto 0); begin + SYSRST <= RESET or PPU_RST_OUT; + serial_peripheral_interface: component spi port map( SYSCLK => SYSCLK, - RESET => RESET, + RESET => SYSRST, DCK => SPI_CLK, DI => SPI_MOSI, - SR => SPI_RESET, + SR => SPI_SR, DO => SPI_DATA, WEN => PPU_WEN); @@ -55,7 +60,7 @@ begin picture_processing_unit: component ppu port map( CLK100 => SYSCLK, - RESET => RESET, + RESET => SYSRST, WEN => PPU_WEN, ADDR => SPI_DATA_ADDR, DATA => SPI_DATA_DATA, @@ -64,5 +69,7 @@ begin B => B, VSYNC => VSYNC, HSYNC => HSYNC, - VBLANK => VBLANK); + VBLANK => VBLANK, + HBLANK => HBLANK, + RESOUT => PPU_RST_OUT); end Behavioral; |