diff options
Diffstat (limited to 'basys3/basys3.srcs/top.vhd')
| -rw-r--r-- | basys3/basys3.srcs/top.vhd | 164 |
1 files changed, 61 insertions, 103 deletions
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index 7cf3e63..558489b 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -1,105 +1,63 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.02.2023 21:09:16 --- Design Name: --- Module Name: top - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values -use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity spiSlave is - Port ( clkBoard : in std_logic; -- clock basys3 100MHz - clkSPI : in std_logic; -- incoming clock of SPI - dataSPI : in std_logic; -- incoming data of SPI - csSPI : in std_logic; -- incoming select of SPI - dataRead : out std_logic_vector(23 downto 0) := (others => '0') -- data read - - ); -end spiSlave; - -architecture Behavioral of spiSlave is - signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI - signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI - signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0'; -- signal for metastability synchronizer of slave select SPI - - signal data : std_logic_vector(23 downto 0) := (others => '0'); -- signal to store incomming data of dataSPI (2x 8bit) - signal counter : integer := 23; --counter for data position - signal enable : std_logic := '0'; -- enable signal if slave is selected +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.ppu_consts.all; + +entity top is port ( + SYSCLK : in std_logic; -- clock basys3 100MHz + RESET : in std_logic; -- global (async) system reset + SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_MOSI : in std_logic; -- incoming data of SPI + SPI_CS : in std_logic; -- incoming select of SPI + WEN : in std_logic; -- PPU VRAM write enable + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + NVSYNC, NHSYNC : out std_logic; -- native VGA out + TVBLANK, THBLANK : out std_logic); -- tiny VGA out +end top; + +architecture Behavioral of top is + component ppu port( + CLK100 : in std_logic; -- system clock + RESET : in std_logic; -- global (async) system reset + EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) + WEN : in std_logic; -- PPU VRAM write enable + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR + DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + NVSYNC, NHSYNC : out std_logic; -- native VGA out + TVBLANK, THBLANK : out std_logic); -- tiny VGA out + end component; + component spi port ( + SYSCLK : in std_logic; -- clock basys3 100MHz + SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_MOSI : in std_logic; -- incoming data of SPI + SPI_CS : in std_logic; -- incoming select of SPI + DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read + end component; + + signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + alias SPI_DATA_ADDR is SPI_DATA(31 downto 16); + alias SPI_DATA_DATA is SPI_DATA(15 downto 0); begin - - process (clkBoard) - begin - - if rising_edge(clkBoard) then - -- flip flop for clk SPI to synchronise a - PulseFF0 <= clkSPI; - PulseFF1 <= PulseFF0; - PulseFF2 <= PulseFF1; - PulseFF3 <= PulseFF2; - -- flip flop for data SPI to synchronise - dataFF0 <= dataSPI; - dataFF1 <= dataFF0; - dataFF2 <= dataFF1; - dataFF3 <= dataFF2; - -- flip flop for slave select SPI to synchronise - ssFF0 <= csSPI; - ssFF1 <= ssFF0; - ssFF2 <= ssFF1; - ssFF3 <= ssFF2; - -- check if slave select signal has falling edge (slave is selected by master) - if(ssFF3 = '1' and ssFF2 = '0') then - --reset counter if true - counter <= 23; - --disable data read if rising edge (slave is not selected) - elsif (ssFF3 = '0' and ssFF2 = '1') then - enable <= '0'; - end if; - --check if synchronised slave select signal is falling edge or data read is enabled - if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then - enable <= '1'; --enable data read - if (PulseFF3 = '0' and PulseFF2 = '1') then -- check for rising edge of clk SPI - if counter > -1 then - counter <= counter - 1; - -- data transfer into vector - data(counter) <= dataFF3; - end if; - end if; - --check if counter is done - if counter = -1 then - counter <= 23; --reset counter - dataRead <= data; - end if; - elsif (enable = '0') then - --dataRead <= data; - - end if; - - end if; - - end process; - + serial_peripheral_interface: component spi port map( + SYSCLK => SYSCLK, + SPI_CLK => SPI_CLK, + SPI_MOSI => SPI_MOSI, + SPI_CS => '1', + DATA => SPI_DATA); + + picture_processing_unit: component ppu port map( + CLK100 => SYSCLK, + RESET => RESET, + EN => '1', + WEN => WEN, + ADDR => SPI_DATA_ADDR, + DATA => SPI_DATA_DATA, + R => R, + G => G, + B => B, + NVSYNC => NVSYNC, + NHSYNC => NHSYNC, + TVBLANK => TVBLANK, + THBLANK => THBLANK); end Behavioral; |