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-rw-r--r--basys3/basys3.srcs/ppu_sprite_transform_tb.vhd32
1 files changed, 16 insertions, 16 deletions
diff --git a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
index cec8c20..516a653 100644
--- a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
@@ -12,18 +12,18 @@ end ppu_sprite_transform_tb;
architecture behavioral of ppu_sprite_transform_tb is
component ppu_sprite_transform port( -- flip sprites
- XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
- YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+ XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+ YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
FLIP_H, FLIP_V : in std_logic; -- flip sprite
- XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
- YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+ XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+ YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
end component;
- signal XI : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
- signal YI : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+ signal XI : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+ signal YI : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
signal FLIP_H, FLIP_V : std_logic := '0';
- signal XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
- signal YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+ signal XO : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+ signal YO : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
begin
uut : component ppu_sprite_transform
port map(
@@ -36,12 +36,12 @@ begin
tb : process
begin
- XI <= std_logic_vector(to_unsigned(4, PPU_SPRITE_POS_H_WIDTH));
- YI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_V_WIDTH));
+ XI <= to_unsigned(4, PPU_SPRITE_POS_H_WIDTH);
+ YI <= to_unsigned(6, PPU_SPRITE_POS_V_WIDTH);
wait for 5 ns;
- XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
- YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+ XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+ YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
wait for 5 ns;
FLIP_H <= '1';
@@ -50,15 +50,15 @@ begin
FLIP_V <= '1';
wait for 5 ns;
- XI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_H_WIDTH));
- YI <= std_logic_vector(to_unsigned(8, PPU_SPRITE_POS_V_WIDTH));
+ XI <= to_unsigned(6, PPU_SPRITE_POS_H_WIDTH);
+ YI <= to_unsigned(8, PPU_SPRITE_POS_V_WIDTH);
wait for 5 ns;
FLIP_H <= '0';
wait for 5 ns;
- XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
- YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+ XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+ YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
wait for 5 ns;
wait; -- stop for simulator