1 files changed, 18 insertions, 7 deletions
diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhd b/basys3/basys3.srcs/ppu_pceg_tb.vhd
index 86061a0..1c2c855 100644
--- a/basys3/basys3.srcs/ppu_pceg_tb.vhd
+++ b/basys3/basys3.srcs/ppu_pceg_tb.vhd
@@ -12,13 +12,15 @@ architecture behavioral of ppu_pceg_tb is
 	component ppu_pceg port(
 		CLK : in std_logic; -- system clock
 		RESET : in std_logic; -- async reset
-		SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch
+		SPRITE_BG : out std_logic; -- sprite info fetch + sprite pixel fetch
+		SPRITE_FG : out std_logic; -- sprite pixel fetch
 		DONE : out std_logic; -- last pipeline stage done
 		READY : out std_logic); -- rgb buffer propagation ready
 	end component;
 	signal CLK : std_logic := '0';
 	signal RESET : std_logic := '0';
-	signal SPRITE : std_logic;
+	signal SPRITE_BG : std_logic;
+	signal SPRITE_FG : std_logic;
 	signal DONE : std_logic;
 	signal READY : std_logic;
 
@@ -26,17 +28,14 @@ begin
 	uut : ppu_pceg port map(
 		CLK => CLK,
 		RESET => RESET,
-		SPRITE => SPRITE,
+		SPRITE_BG => SPRITE_BG,
+		SPRITE_FG => SPRITE_FG,
 		DONE => DONE,
 		READY => READY);
 
 	tb : process
 	begin
 		for i in 0 to 32 loop
-			if i > 20 then
-				RESET <= '1';
-			end if;
-	
 			wait for 5 ns;
 			CLK <= '1';
 			wait for 5 ns;
@@ -44,4 +43,16 @@ begin
 		end loop;
 		wait; -- stop for simulator
 	end process;
+
+	gert : process
+	begin
+		RESET <= '1';
+		wait for 1 ns;
+		RESET <= '0';
+		wait for 100 ns;
+		RESET <= '1';
+		wait for 5 ns;
+		RESET <= '0';
+		wait;
+	end process;
 end;