diff options
Diffstat (limited to 'basys3/basys3.srcs/ppu_pceg.vhd')
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg.vhd | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd index e3c16e8..f87c60d 100644 --- a/basys3/basys3.srcs/ppu_pceg.vhd +++ b/basys3/basys3.srcs/ppu_pceg.vhd @@ -9,8 +9,7 @@ entity ppu_pceg is port( SPRITE_BG : out ppu_sprite_bg_pl_state := PL_BG_IDLE; -- sprite info fetch + sprite pixel fetch SPRITE_FG : out ppu_sprite_fg_pl_state := PL_FG_IDLE; -- sprite pixel fetch SPRITE_FG_HIT : out ppu_sprite_fg_hit_pl_state := PL_HIT_INACCURATE; -- foreground hit accuracy - DONE : out std_logic; -- last pipeline stage done - READY : out std_logic); -- rgb buffer propagation ready + DISPCTL_BWEN : out std_logic := '0'); -- display controller scanline buffer write enable end ppu_pceg; architecture Behavioral of ppu_pceg is @@ -24,38 +23,32 @@ begin SPRITE_BG <= PL_BG_IDLE; SPRITE_FG <= PL_FG_IDLE; - DONE <= '0'; - READY <= '0'; + DISPCTL_BWEN <= '0'; elsif falling_edge(CLK) then case CLK_IDX is when 0 => - DONE <= '0'; - READY <= '0'; + DISPCTL_BWEN <= '0'; SPRITE_BG <= PL_BG_IDLE; SPRITE_FG <= PL_FG_IDLE; SPRITE_FG_HIT <= PL_HIT_INACCURATE; when 1 => SPRITE_BG <= PL_BG_BAM_ADDR; SPRITE_FG <= PL_FG_TMM_ADDR; - when 3 => - SPRITE_BG <= PL_BG_IDLE; - SPRITE_FG <= PL_FG_IDLE; - when 4 => + when 2 => SPRITE_BG <= PL_BG_BAM_DATA; SPRITE_FG <= PL_FG_TMM_DATA; - when 5 => + when 3 => SPRITE_BG <= PL_BG_TMM_ADDR; SPRITE_FG <= PL_FG_IDLE; SPRITE_FG_HIT <= PL_HIT_ACCURATE; - when 6 => null; - when 7 => - SPRITE_BG <= PL_BG_IDLE; - when 8 => - DONE <= '1'; + when 4 => SPRITE_BG <= PL_BG_TMM_DATA; - when 9 => + when 5 => SPRITE_BG <= PL_BG_IDLE; - READY <= '1'; + when 6 => + DISPCTL_BWEN <= '1'; + when 7 => + DISPCTL_BWEN <= '0'; when others => null; end case; |