1 files changed, 5 insertions, 18 deletions

diff --git a/basys3/basys3.srcs/ppu_dispctl_tb.vhd b/basys3/basys3.srcs/ppu_dispctl_tb.vhd
index fa11655..deb3d48 100644
--- a/basys3/basys3.srcs/ppu_dispctl_tb.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl_tb.vhd
@@ -10,20 +10,7 @@ entity ppu_dispctl_tb is
 end ppu_dispctl_tb;
 
 architecture behavioral of ppu_dispctl_tb is
-	component ppu_dispctl port(
-		CLK : in std_logic; -- system clock
-		RESET : in std_logic;
-
-		X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x
-		Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y
-		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in
-		PREADY : in std_logic; -- current pixel ready (pixel color is stable)
-
-		RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-		NVSYNC, NHSYNC : out std_logic; -- VGA sync out
-		THBLANK, TVBLANK : out std_logic); -- tiny sync signals
-	end component;
-	signal CLK : std_logic := '0';
+	signal SYSCLK : std_logic := '0';
 	signal RESET : std_logic := '0';
 	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
 	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
@@ -33,8 +20,8 @@ architecture behavioral of ppu_dispctl_tb is
 	signal NVSYNC, NHSYNC : std_logic := '0';
 	signal THBLANK, TVBLANK : std_logic := '0';
 begin
-	uut : component ppu_dispctl port map(
-		CLK => CLK,
+	uut : entity work.ppu_dispctl port map(
+		SYSCLK => SYSCLK,
 		RESET => RESET,
 		PREADY => PREADY,
 		X => X,
@@ -54,9 +41,9 @@ begin
 	begin
 		for i in 0 to 3200000 loop
 			wait for 5 ps;
-			CLK <= '1';
+			SYSCLK <= '1';
 			wait for 5 ps;
-			CLK <= '0';
+			SYSCLK <= '0';
 		end loop;
 		wait; -- stop for simulator
 	end process;