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Diffstat (limited to 'basys3/basys3.srcs/ppu_dispctl.vhd')
-rw-r--r--basys3/basys3.srcs/ppu_dispctl.vhd12
1 files changed, 6 insertions, 6 deletions
diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
index 117b780..1d3d922 100644
--- a/basys3/basys3.srcs/ppu_dispctl.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -20,10 +20,10 @@ end ppu_dispctl;
architecture Behavioral of ppu_dispctl is
component ppu_dispctl_pixclk is port (
- clk_out1 : out std_logic;
- clk_out2 : out std_logic;
+ npxclk : out std_logic;
+ tpxclk : out std_logic;
reset : in std_logic;
- clk_in1 : in std_logic);
+ sysclk : in std_logic);
end component;
component ppu_dispctl_slbuf port( -- scanline buffer
clka : in std_logic;
@@ -159,8 +159,8 @@ begin
rstb_busy => open);
pixel_clock: component ppu_dispctl_pixclk port map(
- clk_in1 => SYSCLK,
+ sysclk => SYSCLK,
reset => RESET,
- clk_out1 => NPIXCLK,
- clk_out2 => TPIXCLK);
+ npxclk => NPIXCLK,
+ tpxclk => TPIXCLK);
end Behavioral;