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-rw-r--r--basys3/basys3.srcs/ppu.vhd16
1 files changed, 8 insertions, 8 deletions
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 28134c6..663f3ab 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -188,14 +188,14 @@ begin
SYSCLK <= CLK100;
SYSRST <= RESET;
- -- internal unused lines
- --
- -- these lines would be used if components use memory blocks as RAM blocks
- -- (like how TMM and BAM work), the registers of these memory regions are
- -- directly exposed internally, and are as such not used as RAM blocks
- AUX_AI <= (others => '0');
- FAM_AI <= (others => '0');
- PAL_AI <= (others => '0');
+ -- internal unused lines
+ --
+ -- these lines would be used if components use memory blocks as RAM blocks
+ -- (like how TMM and BAM work), the registers of these memory regions are
+ -- directly exposed internally, and are as such not used as RAM blocks
+ AUX_AI <= (others => '0');
+ FAM_AI <= (others => '0');
+ PAL_AI <= (others => '0');
pipeline_clock_edge_generator: component ppu_pceg port map(
CLK => SYSCLK,