diff options
Diffstat (limited to 'basys3/basys3.srcs/apu_lut_reader.vhd')
-rw-r--r-- | basys3/basys3.srcs/apu_lut_reader.vhd | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/basys3/basys3.srcs/apu_lut_reader.vhd b/basys3/basys3.srcs/apu_lut_reader.vhd index 2f92eca..b3b0ca4 100644 --- a/basys3/basys3.srcs/apu_lut_reader.vhd +++ b/basys3/basys3.srcs/apu_lut_reader.vhd @@ -2,20 +2,23 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.apu_consts.all; + entity apu_lut_reader is port ( clk : in std_logic; rst : in std_logic; freq : in std_logic_vector(11 downto 0); wave : in std_logic_vector(1 downto 0); - value : out std_logic_vector(7 downto 0) + value : out std_logic_vector(SAMPLE_SIZE_WIDTH-1 downto 0) ); end entity; architecture behavioral of apu_lut_reader is - constant AMPLITUDE : natural := 0; - constant SAMPLE_SIZE : natural := 256; + -- amplitude (currently) only applies to square waves + constant AMPLITUDE : natural := SAMPLE_SIZE/2; -- less or equals SAMPLE_SIZE/2 (Amplitude around SAMPLE_SIZE/2) signal idx : unsigned := (others => '0'); signal buf : unsigned := (others => '0'); @@ -23,6 +26,9 @@ architecture behavioral of apu_lut_reader is begin process (clk) + variable val_min : unsigned := to_unsigned(SAMPLE_SIZE/2 - integer(AMPLITUDE),SAMPLE_SIZE_WIDTH-1); + variable val_max : unsigned := to_unsigned(SAMPLE_SIZE/2 + integer(AMPLITUDE),SAMPLE_SIZE_WIDTH-1); + begin if rst = '1' then idx <= x"00"; @@ -35,9 +41,9 @@ begin value <= std_logic_vector( idx ); elsif wave = "01" then -- Square if idx < (SAMPLE_SIZE/2) then - value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave) + value <= std_logic_vector(val_min); --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave) else - value <= x"FF"; + value <= std_logic_vector(val_max); end if; elsif wave = "10" then -- Triangle if idx < (SAMPLE_SIZE/2) then |