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-rw-r--r--src/main.c2
-rw-r--r--src/main.h3
-rw-r--r--src/ppu/stm.c2
-rw-r--r--src/stm32/consts.h42
-rw-r--r--src/stm32/input.c18
-rw-r--r--src/stm32/main.c7
-rw-r--r--src/stm32/setup.c65
-rw-r--r--src/stm32/setup.h5
-rw-r--r--test/conntest/.gitignore8
-rw-r--r--test/conntest/conntest.srcs/io.xdc94
-rw-r--r--test/conntest/conntest.srcs/top.vhd32
-rw-r--r--test/conntest/conntest.xpr236
12 files changed, 488 insertions, 26 deletions
diff --git a/src/main.c b/src/main.c
index a3a4351..67490ab 100644
--- a/src/main.c
+++ b/src/main.c
@@ -6,6 +6,8 @@
#include "ppu/internals.h"
bool g_hh_run = true;
+volatile unsigned long g_hh_vcount;
+volatile unsigned short g_hh_hcount;
void hh_ppu_vblank_interrupt() {
static unsigned long frame = 0;
diff --git a/src/main.h b/src/main.h
index 8e94f18..b2003d3 100644
--- a/src/main.h
+++ b/src/main.h
@@ -2,6 +2,9 @@
#include <stdbool.h>
+extern volatile unsigned long g_hh_vcount;
+extern volatile unsigned short g_hh_hcount;
+
extern bool g_hh_run;
/** @brief exec entrypoint */
diff --git a/src/ppu/stm.c b/src/ppu/stm.c
index 72e46ae..e1d7e5d 100644
--- a/src/ppu/stm.c
+++ b/src/ppu/stm.c
@@ -18,6 +18,8 @@ void hh_ppu_vram_dwrite(uint8_t* data, size_t size) {
HAL_SPI_Transmit(&hspi1, (uint8_t[4]){ 0xff }, 4, HAL_MAX_DELAY);
// reset SPI
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
+ // HAL_Delay(100); // TODO: remove
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
+ // HAL_Delay(100); // TODO: remove
}
diff --git a/src/stm32/consts.h b/src/stm32/consts.h
new file mode 100644
index 0000000..447e36e
--- /dev/null
+++ b/src/stm32/consts.h
@@ -0,0 +1,42 @@
+#pragma once
+
+#include <stm32f091xc.h>
+
+// ../../docs/hardware/pinout.md
+#define HH_IO_SPI_PORT GPIOA
+#define HH_IO_SPI_PINS (GPIO_PIN_5 | GPIO_PIN_7)
+
+#define HH_IO_SPI_SR_PORT GPIOA
+#define HH_IO_SPI_SR_PIN GPIO_PIN_9
+
+#define HH_IO_PPU_HBLANK_PORT GPIOA
+#define HH_IO_PPU_HBLANK_PIN GPIO_PIN_8
+#define HH_IO_PPU_VBLANK_PORT GPIOC
+#define HH_IO_PPU_VBLANK_PIN GPIO_PIN_7
+
+#define HH_IO_GP1_UP_PORT GPIOB
+#define HH_IO_GP1_UP_PIN GPIO_PIN_5
+#define HH_IO_GP1_DOWN_PORT GPIOA
+#define HH_IO_GP1_DOWN_PIN GPIO_PIN_3
+#define HH_IO_GP1_LEFT_PORT GPIOB
+#define HH_IO_GP1_LEFT_PIN GPIO_PIN_3
+#define HH_IO_GP1_RIGHT_PORT GPIOB
+#define HH_IO_GP1_RIGHT_PIN GPIO_PIN_4
+#define HH_IO_GP1_PRIMARY_PORT GPIOA
+#define HH_IO_GP1_PRIMARY_PIN GPIO_PIN_10
+#define HH_IO_GP1_SECONDARY_PORT GPIOA
+#define HH_IO_GP1_SECONDARY_PIN GPIO_PIN_2
+
+#define HH_IO_GP2_UP_PORT GPIOC
+#define HH_IO_GP2_UP_PIN GPIO_PIN_1
+#define HH_IO_GP2_DOWN_PORT GPIOA
+#define HH_IO_GP2_DOWN_PIN GPIO_PIN_0
+#define HH_IO_GP2_LEFT_PORT GPIOB
+#define HH_IO_GP2_LEFT_PIN GPIO_PIN_0
+#define HH_IO_GP2_PRIMARY_PORT GPIOC
+#define HH_IO_GP2_PRIMARY_PIN GPIO_PIN_0
+#define HH_IO_GP2_RIGHT_PORT GPIOA
+#define HH_IO_GP2_RIGHT_PIN GPIO_PIN_4
+#define HH_IO_GP2_SECONDARY_PORT GPIOA
+#define HH_IO_GP2_SECONDARY_PIN GPIO_PIN_1
+
diff --git a/src/stm32/input.c b/src/stm32/input.c
index e2d07cb..ee1a262 100644
--- a/src/stm32/input.c
+++ b/src/stm32/input.c
@@ -1,13 +1,23 @@
#include <stm32f0xx_hal_gpio.h>
#include "input.h"
+#include "stm32/consts.h"
hh_s_gamepad g_hh_controller_p1 = { 0 };
hh_s_gamepad g_hh_controller_p2 = { 0 };
void hh_input_read() {
- g_hh_controller_p1.dpad_left = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_4);
- g_hh_controller_p1.dpad_right = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_5);
- g_hh_controller_p1.dpad_down = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_6);
- g_hh_controller_p1.dpad_up = HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_8);
+ g_hh_controller_p1.dpad_up = HAL_GPIO_ReadPin(HH_IO_GP1_UP_PORT, HH_IO_GP1_UP_PIN);
+ g_hh_controller_p1.dpad_down = HAL_GPIO_ReadPin(HH_IO_GP1_DOWN_PORT, HH_IO_GP1_DOWN_PIN);
+ g_hh_controller_p1.dpad_left = HAL_GPIO_ReadPin(HH_IO_GP1_LEFT_PORT, HH_IO_GP1_LEFT_PIN);
+ g_hh_controller_p1.dpad_right = HAL_GPIO_ReadPin(HH_IO_GP1_RIGHT_PORT, HH_IO_GP1_RIGHT_PIN);
+ g_hh_controller_p1.button_primary = HAL_GPIO_ReadPin(HH_IO_GP1_PRIMARY_PORT, HH_IO_GP1_PRIMARY_PIN);
+ g_hh_controller_p1.button_secondary = HAL_GPIO_ReadPin(HH_IO_GP1_SECONDARY_PORT, HH_IO_GP1_SECONDARY_PIN);
+
+ g_hh_controller_p2.dpad_up = HAL_GPIO_ReadPin(HH_IO_GP2_UP_PORT, HH_IO_GP2_UP_PIN);
+ g_hh_controller_p2.dpad_down = HAL_GPIO_ReadPin(HH_IO_GP2_DOWN_PORT, HH_IO_GP2_DOWN_PIN);
+ g_hh_controller_p2.dpad_left = HAL_GPIO_ReadPin(HH_IO_GP2_LEFT_PORT, HH_IO_GP2_LEFT_PIN);
+ g_hh_controller_p2.dpad_right = HAL_GPIO_ReadPin(HH_IO_GP2_RIGHT_PORT, HH_IO_GP2_RIGHT_PIN);
+ g_hh_controller_p2.button_primary = HAL_GPIO_ReadPin(HH_IO_GP2_PRIMARY_PORT, HH_IO_GP2_PRIMARY_PIN);
+ g_hh_controller_p2.button_secondary = HAL_GPIO_ReadPin(HH_IO_GP2_SECONDARY_PORT, HH_IO_GP2_SECONDARY_PIN);
}
diff --git a/src/stm32/main.c b/src/stm32/main.c
index fb548d8..b7b4604 100644
--- a/src/stm32/main.c
+++ b/src/stm32/main.c
@@ -1,14 +1,9 @@
#include <stm32f0xx_hal.h>
#include "main.h"
-#include "ppu/ppu.h"
void hh_ppu_load_tilemap() {}
void hh_loop() {
- // TODO: call hh_ppu_vblank_interrupt on interrupt instead of manually
- while (1) {
- hh_ppu_vblank_interrupt();
- HAL_Delay(16);
- }
+ while(1);
}
diff --git a/src/stm32/setup.c b/src/stm32/setup.c
index 9de1f48..f692159 100644
--- a/src/stm32/setup.c
+++ b/src/stm32/setup.c
@@ -9,6 +9,7 @@
#include "setup.h"
#include "demo.h"
#include "ppu/ppu.h"
+#include "stm32/consts.h"
UART_HandleTypeDef huart2 = {
.Instance = USART2,
@@ -131,22 +132,44 @@ void hh_io_tim_setup() {
}) != HAL_OK) return hh_io_setup_error_handler();
}
+static void gpio_init(GPIO_TypeDef* port, uint16_t pin, uint32_t mode, uint32_t pull) {
+ HAL_GPIO_Init(port, &(GPIO_InitTypeDef) {
+ .Pin = pin,
+ .Mode = mode,
+ .Pull = pull,
+ .Speed = GPIO_SPEED_FREQ_HIGH,
+ });
+}
+
void hh_io_gpio_setup() {
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
-
- HAL_GPIO_Init(GPIOA, &(GPIO_InitTypeDef) {
- .Pin = GPIO_PIN_9,
- .Mode = GPIO_MODE_OUTPUT_PP,
- .Pull = GPIO_NOPULL,
- .Speed = GPIO_SPEED_FREQ_HIGH,
- });
- HAL_GPIO_Init(GPIOA, &(GPIO_InitTypeDef) {
- .Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_8,
- .Mode = GPIO_MODE_INPUT,
- .Pull = GPIO_PULLDOWN,
- });
- HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+
+ // SPI reset line
+ gpio_init(HH_IO_SPI_SR_PORT, HH_IO_SPI_SR_PIN, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL);
+
+ // PPU HBLANK/VBLANK
+ gpio_init(HH_IO_PPU_HBLANK_PORT, HH_IO_PPU_HBLANK_PIN, GPIO_MODE_IT_RISING, GPIO_NOPULL);
+ gpio_init(HH_IO_PPU_VBLANK_PORT, HH_IO_PPU_VBLANK_PIN, GPIO_MODE_IT_RISING, GPIO_NOPULL);
+ HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
+
+ // gamepad 1
+ gpio_init(HH_IO_GP1_UP_PORT, HH_IO_GP1_UP_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP1_DOWN_PORT, HH_IO_GP1_DOWN_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP1_LEFT_PORT, HH_IO_GP1_LEFT_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP1_RIGHT_PORT, HH_IO_GP1_RIGHT_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP1_PRIMARY_PORT, HH_IO_GP1_PRIMARY_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP1_SECONDARY_PORT, HH_IO_GP1_SECONDARY_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+
+ // gamepad 2
+ gpio_init(HH_IO_GP2_UP_PORT, HH_IO_GP2_UP_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP2_DOWN_PORT, HH_IO_GP2_DOWN_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP2_LEFT_PORT, HH_IO_GP2_LEFT_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP2_RIGHT_PORT, HH_IO_GP2_RIGHT_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP2_PRIMARY_PORT, HH_IO_GP2_PRIMARY_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
+ gpio_init(HH_IO_GP2_SECONDARY_PORT, HH_IO_GP2_SECONDARY_PIN, GPIO_MODE_INPUT, GPIO_PULLDOWN);
}
void HAL_MspInit() {
@@ -199,3 +222,19 @@ void hh_io_setup_error_handler() {
__disable_irq();
while (1);
}
+
+void EXTI4_15_IRQHandler() {
+ HAL_GPIO_EXTI_IRQHandler(HH_IO_PPU_HBLANK_PIN);
+ HAL_GPIO_EXTI_IRQHandler(HH_IO_PPU_VBLANK_PIN);
+}
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
+ if (GPIO_Pin == HH_IO_PPU_HBLANK_PIN) {
+ g_hh_hcount++;
+ }
+ if (GPIO_Pin == HH_IO_PPU_VBLANK_PIN) {
+ g_hh_hcount = 0;
+ g_hh_vcount++;
+ hh_ppu_vblank_interrupt();
+ }
+}
diff --git a/src/stm32/setup.h b/src/stm32/setup.h
index 66d5ff3..b9432dc 100644
--- a/src/stm32/setup.h
+++ b/src/stm32/setup.h
@@ -5,9 +5,6 @@
#include <stm32f0xx_hal_tim.h>
#include <stm32f0xx_hal_gpio.h>
-#define HH_IO_SPI_PINS (GPIO_PIN_5 | GPIO_PIN_7)
-#define HH_IO_SPI_PORT GPIOA
-
extern UART_HandleTypeDef huart2; // NOLINT
extern GPIO_InitTypeDef spi_gpio; // NOLINT
extern SPI_HandleTypeDef hspi1; // NOLINT
@@ -22,3 +19,5 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base); // NOLINT
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base); // NOLINT
void HardFault_Handler(); // NOLINT
void SysTick_Handler(); // NOLINT
+void EXTI4_15_IRQHandler(); // NOLINT
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); // NOLINT
diff --git a/test/conntest/.gitignore b/test/conntest/.gitignore
new file mode 100644
index 0000000..262a2cc
--- /dev/null
+++ b/test/conntest/.gitignore
@@ -0,0 +1,8 @@
+*.cache
+*.hw
+*.ioplanning
+*.ip_user_files
+*.runs
+*.sim
+*.gen
+*.dcp
diff --git a/test/conntest/conntest.srcs/io.xdc b/test/conntest/conntest.srcs/io.xdc
new file mode 100644
index 0000000..ae8e63d
--- /dev/null
+++ b/test/conntest/conntest.srcs/io.xdc
@@ -0,0 +1,94 @@
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
+set_property PACKAGE_PIN L2 [get_ports SPI_MOSI]
+
+set_property PACKAGE_PIN J2 [get_ports SPI_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
+
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_SR]
+set_property PACKAGE_PIN H1 [get_ports SPI_SR]
+set_property PULLDOWN true [get_ports SPI_SR]
+
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports HBLANK]
+set_property PACKAGE_PIN K2 [get_ports HBLANK]
+
+set_property IOSTANDARD LVCMOS33 [get_ports VBLANK]
+set_property PACKAGE_PIN J1 [get_ports VBLANK]
+
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]
+set_property PACKAGE_PIN W5 [get_ports SYSCLK]
+
+set_property IOSTANDARD LVCMOS33 [get_ports RESET]
+set_property PACKAGE_PIN T18 [get_ports RESET]
+
+set_property IOSTANDARD LVCMOS33 [get_ports DBG_DISP_ADDR]
+set_property PACKAGE_PIN R2 [get_ports DBG_DISP_ADDR]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_LEDS_OUT[0]}]
+set_property PACKAGE_PIN L1 [get_ports {DBG_LEDS_OUT[15]}]
+set_property PACKAGE_PIN P1 [get_ports {DBG_LEDS_OUT[14]}]
+set_property PACKAGE_PIN N3 [get_ports {DBG_LEDS_OUT[13]}]
+set_property PACKAGE_PIN P3 [get_ports {DBG_LEDS_OUT[12]}]
+set_property PACKAGE_PIN U3 [get_ports {DBG_LEDS_OUT[11]}]
+set_property PACKAGE_PIN W3 [get_ports {DBG_LEDS_OUT[10]}]
+set_property PACKAGE_PIN V3 [get_ports {DBG_LEDS_OUT[9]}]
+set_property PACKAGE_PIN V13 [get_ports {DBG_LEDS_OUT[8]}]
+set_property PACKAGE_PIN V14 [get_ports {DBG_LEDS_OUT[7]}]
+set_property PACKAGE_PIN U14 [get_ports {DBG_LEDS_OUT[6]}]
+set_property PACKAGE_PIN U15 [get_ports {DBG_LEDS_OUT[5]}]
+set_property PACKAGE_PIN W18 [get_ports {DBG_LEDS_OUT[4]}]
+set_property PACKAGE_PIN V19 [get_ports {DBG_LEDS_OUT[3]}]
+set_property PACKAGE_PIN U19 [get_ports {DBG_LEDS_OUT[2]}]
+set_property PACKAGE_PIN E19 [get_ports {DBG_LEDS_OUT[1]}]
+set_property PACKAGE_PIN U16 [get_ports {DBG_LEDS_OUT[0]}]
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {DBG_SWTC_IN[0]}]
+set_property PACKAGE_PIN R2 [get_ports {DBG_SWTC_IN[15]}]
+set_property PACKAGE_PIN T1 [get_ports {DBG_SWTC_IN[14]}]
+set_property PACKAGE_PIN U1 [get_ports {DBG_SWTC_IN[13]}]
+set_property PACKAGE_PIN W2 [get_ports {DBG_SWTC_IN[12]}]
+set_property PACKAGE_PIN R3 [get_ports {DBG_SWTC_IN[11]}]
+set_property PACKAGE_PIN T2 [get_ports {DBG_SWTC_IN[10]}]
+set_property PACKAGE_PIN T3 [get_ports {DBG_SWTC_IN[9]}]
+set_property PACKAGE_PIN V2 [get_ports {DBG_SWTC_IN[8]}]
+set_property PACKAGE_PIN W13 [get_ports {DBG_SWTC_IN[7]}]
+set_property PACKAGE_PIN W14 [get_ports {DBG_SWTC_IN[6]}]
+set_property PACKAGE_PIN V15 [get_ports {DBG_SWTC_IN[5]}]
+set_property PACKAGE_PIN W15 [get_ports {DBG_SWTC_IN[4]}]
+set_property PACKAGE_PIN W17 [get_ports {DBG_SWTC_IN[3]}]
+set_property PACKAGE_PIN W16 [get_ports {DBG_SWTC_IN[2]}]
+set_property PACKAGE_PIN V16 [get_ports {DBG_SWTC_IN[1]}]
+set_property PACKAGE_PIN V17 [get_ports {DBG_SWTC_IN[0]}]
diff --git a/test/conntest/conntest.srcs/top.vhd b/test/conntest/conntest.srcs/top.vhd
new file mode 100644
index 0000000..68c4864
--- /dev/null
+++ b/test/conntest/conntest.srcs/top.vhd
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top is port (
+ SYSCLK : in std_logic; -- clock basys3 100MHz
+ RESET : in std_logic; -- global (async) system reset
+ SPI_CLK, SPI_MOSI, SPI_SR : in std_logic;
+ DBG_SWTC_IN : in std_logic_vector(15 downto 0); -- switches
+ DBG_LEDS_OUT : out std_logic_vector(15 downto 0); -- leds
+ VBLANK, HBLANK : out std_logic); -- vblank for synchronization
+end top;
+
+architecture Behavioral of top is
+begin
+ process(SYSCLK, RESET)
+ begin
+ if RESET = '1' then
+ VBLANK <= '0';
+ HBLANK <= '0';
+ DBG_LEDS_OUT(15) <= '0';
+ DBG_LEDS_OUT(14) <= '0';
+ DBG_LEDS_OUT(13) <= '0';
+ elsif rising_edge(SYSCLK) then
+ VBLANK <= DBG_SWTC_IN(0);
+ HBLANK <= DBG_SWTC_IN(1);
+ DBG_LEDS_OUT(15) <= SPI_SR;
+ DBG_LEDS_OUT(14) <= SPI_CLK;
+ DBG_LEDS_OUT(13) <= SPI_MOSI;
+ end if;
+ end process;
+end Behavioral;
diff --git a/test/conntest/conntest.xpr b/test/conntest/conntest.xpr
new file mode 100644
index 0000000..2af538a
--- /dev/null
+++ b/test/conntest/conntest.xpr
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="61" Path="/home/loek/docs/repos/avans-arcade/test/conntest/conntest.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="2282f4b3892442a18aaeab83aaf566df"/>
+ <Option Name="Part" Val="xc7a35tcpg236-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+ <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+ <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+ <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+ <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+ <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="basys3"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/top.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="top"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/io.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/io.xdc"/>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="top"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="19">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>