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-rw-r--r--basys3/basys3.srcs/apu_LUT_reader.vhd56
-rw-r--r--basys3/basys3.srcs/apu_tb_LUT_reader.vhd48
2 files changed, 104 insertions, 0 deletions
diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd
new file mode 100644
index 0000000..2dd3b06
--- /dev/null
+++ b/basys3/basys3.srcs/apu_LUT_reader.vhd
@@ -0,0 +1,56 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity apu_LUT_reader is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ freq : in std_logic_vector(11 downto 0);
+ wave : in std_logic_vector(1 downto 0);
+ value : out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture Behavioral of apu_LUT_reader is
+
+ signal idx : std_logic_vector(7 downto 0) := (others => '0');
+ signal buf : unsigned := (others => '0');
+
+begin
+
+ process (clk)
+ begin
+ if rst = '1' then
+ idx <= x"00";
+ buf <= x"00";
+ elsif rising_edge(clk) then
+ --main code here
+
+ if wave = "00" then --Sawtooth
+ value <= idx;
+ elsif wave = "01" then --Square
+ if (signed(idx) < 128) then
+ value <= x"00";
+ else
+ value <= x"FF";
+ end if;
+ elsif wave = "10" then --Triangle
+ value <= std_logic_vector( abs(signed(idx)-127)*2 );
+ else--wave = "11" then --Noise
+ --implement noise function here:
+ value <= x"80"; --remove this
+ end if;
+
+
+
+ if unsigned(idx) < 255 then --moves to next index value
+ idx <= std_logic_vector( unsigned(idx) + '1');
+ else
+ idx <= x"00";
+ end if;
+
+ end if;
+ end process;
+
+end architecture; \ No newline at end of file
diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
new file mode 100644
index 0000000..d4ed935
--- /dev/null
+++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity apu_tb_LUT_reader is
+end entity;
+
+architecture Behavioral of apu_tb_LUT_reader is
+ component apu_LUT_reader is
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ freq : in std_logic_vector(11 downto 0);
+ wave : in std_logic_vector(1 downto 0);
+ value : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ signal OK : boolean := false;
+
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal freq : std_logic_vector(11 downto 0) := (others => '0');
+ signal wave : std_logic_vector(1 downto 0) := (others => '0');
+
+begin
+
+ TB: process
+ begin
+ wave <= "00";
+ for I in 0 to 255 loop
+ clk <= '1';
+
+ -- freq <= '1';
+
+
+ wait for 1 ps;
+ clk <= '0';
+ wait for 1 ps;
+
+
+ end loop;
+ end process;
+
+end architecture; \ No newline at end of file