diff options
| -rw-r--r-- | basys3/basys3.srcs/apu.vhd | 32 | ||||
| -rw-r--r-- | basys3/basys3.srcs/apu_note_to_frequency.vhd | 6 | ||||
| -rw-r--r-- | basys3/basys3.srcs/apu_note_to_frequency_tb.vhd | 14 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu.vhd | 266 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_addr_dec.vhd | 30 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_addr_dec_tb.vhd | 60 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_consts.vhd | 38 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg.vhd | 16 | ||||
| -rw-r--r-- | basys3/basys3.srcs/ppu_pceg_tb.vhd | 24 | ||||
| -rw-r--r-- | style.md | 1 |
10 files changed, 244 insertions, 243 deletions
diff --git a/basys3/basys3.srcs/apu.vhd b/basys3/basys3.srcs/apu.vhd index 4a594ab..1fff1e8 100644 --- a/basys3/basys3.srcs/apu.vhd +++ b/basys3/basys3.srcs/apu.vhd @@ -3,29 +3,29 @@ use ieee.std_logic_1164.all; --use ieee.numeric_std.all; entity apu is port( - CLK100: in std_logic; -- system clock - RESET: in std_logic; -- global (async) system reset - DATA: in std_logic_vector(15 downto 0); - SOUND: out std_logic); + CLK100 : in std_logic; -- system clock + RESET : in std_logic; -- global (async) system reset + DATA : in std_logic_vector(15 downto 0); + SOUND : out std_logic); - -- EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) - -- WEN: in std_logic; -- PPU VRAM write enable - -- ADDR: in std_logic_vector(15 downto 0); -- PPU VRAM ADDR - -- R,G,B: out std_logic_vector(3 downto 0); - -- NVSYNC, NHSYNC: out std_logic; -- native VGA out - -- TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out + -- EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) + -- WEN : in std_logic; -- PPU VRAM write enable + -- ADDR : in std_logic_vector(15 downto 0); -- PPU VRAM ADDR + -- R,G,B : out std_logic_vector(3 downto 0); + -- NVSYNC, NHSYNC : out std_logic; -- native VGA out + -- TVSYNC, TVBLANK, THSYNC, THBLANK : out std_logic); -- tiny VGA out end apu; architecture Behavioral of apu is component apu_note_to_frequency port( - data: in std_logic_vector(7 downto 0); - freq: out std_logic_vector(7 downto 0)); --frequency + data : in std_logic_vector(7 downto 0); + freq : out std_logic_vector(7 downto 0)); --frequency end component; component apu_LUT_reader port( - clk: in std_logic; - rst: in std_logic; - wave: in std_logic_vector(1 downto 0); - level: out std_logic_vector(7 downto 0)); + clk : in std_logic; + rst : in std_logic; + wave : in std_logic_vector(1 downto 0); + level : out std_logic_vector(7 downto 0)); end component; begin diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd index 7e02c75..1e47b8e 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd @@ -10,9 +10,9 @@ entity apu_note_to_frequency is port ( end entity; architecture Behavioral of apu_note_to_frequency is - signal buff_small: std_logic_vector(7 downto 0) := (others => '0'); - signal buff: std_logic_vector(15 downto 0) := (others => '0'); - signal shift: integer; + signal buff_small : std_logic_vector(7 downto 0) := (others => '0'); + signal buff : std_logic_vector(15 downto 0) := (others => '0'); + signal shift : integer; begin shift <= to_integer(unsigned(data(2 downto 0))); buff_small <= diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd index 6814c1f..f48a40c 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd @@ -10,20 +10,20 @@ end entity; architecture Behavioral of apu_note_to_frequency_tb is component apu_note_to_frequency is port( - data: in std_logic_vector(7 downto 0); - freq: out std_logic_vector(11 downto 0)); -- frequency + data : in std_logic_vector(7 downto 0); + freq : out std_logic_vector(11 downto 0)); -- frequency end component; - signal data: std_logic_vector(7 downto 0) := (others => '0'); - signal freq: std_logic_vector(11 downto 0) := (others => '0'); + signal data : std_logic_vector(7 downto 0) := (others => '0'); + signal freq : std_logic_vector(11 downto 0) := (others => '0'); - signal ok: boolean := false; + signal ok : boolean := false; begin - uut: apu_note_to_frequency port map( + uut : apu_note_to_frequency port map( data => data, freq => freq); - tb: process + tb : process begin for i in 0 to 255 loop data <= std_logic_vector(to_unsigned(i, 8)); diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd index 663f3ab..acf546f 100644 --- a/basys3/basys3.srcs/ppu.vhd +++ b/basys3/basys3.srcs/ppu.vhd @@ -6,184 +6,184 @@ use ieee.std_logic_1164.all; use work.ppu_consts.all; entity ppu is port( - CLK100: in std_logic; -- system clock - RESET: in std_logic; -- global (async) system reset - EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) - WEN: in std_logic; -- PPU VRAM write enable - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR - DATA: in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); - R,G,B: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); - NVSYNC, NHSYNC: out std_logic; -- native VGA out - TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out + CLK100 : in std_logic; -- system clock + RESET : in std_logic; -- global (async) system reset + EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers) + WEN : in std_logic; -- PPU VRAM write enable + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR + DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0); + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); + NVSYNC, NHSYNC : out std_logic; -- native VGA out + TVSYNC, TVBLANK, THSYNC, THBLANK : out std_logic); -- tiny VGA out end ppu; architecture Behavioral of ppu is component ppu_pceg port( -- pipeline clock edge generator - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done + CLK : in std_logic; -- system clock + RESET : in std_logic; -- async reset + SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch + COMP_PAL : out std_logic; -- compositor + palette lookup + DONE : out std_logic); -- last pipeline stage done end component; component ppu_addr_dec port( -- pipeline clock edge generator - WEN: in std_logic; -- EXT write enable + WEN : in std_logic; -- EXT write enable TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, - AUX_WEN: out std_logic; -- write enable MUX - EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in - TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); + AUX_WEN : out std_logic; -- write enable MUX + EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in + TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); end component; component ppu_bam port( -- BAM block memory - clka: in std_logic; - rsta: in std_logic; - wea: in std_logic_vector(0 downto 0); - addra: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - dina: in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); - douta: out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); - rsta_busy: out std_logic); + clka : in std_logic; + rsta : in std_logic; + wea : in std_logic_vector(0 downto 0); + addra : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + dina : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); + douta : out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); + rsta_busy : out std_logic); end component; component ppu_tmm port( -- TMM block memory - clka: in std_logic; - rsta: in std_logic; - wea: in std_logic_vector(0 downto 0); - addra: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - dina: in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); - douta: out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); - rsta_busy: out std_logic); + clka : in std_logic; + rsta : in std_logic; + wea : in std_logic_vector(0 downto 0); + addra : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + dina : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); + douta : out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); + rsta_busy : out std_logic); end component; component ppu_aux port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- reset memory + CLK : in std_logic; -- system clock + RESET : in std_logic; -- reset memory -- internal memory block (AUX) - AUX_WEN: in std_logic; -- VRAM AUX write enable - AUX_ADDR: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address - AUX_DATA: in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data + AUX_WEN : in std_logic; -- VRAM AUX write enable + AUX_ADDR : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address + AUX_DATA : in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data -- aux outputs - BG_SHIFT_X: out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); - BG_SHIFT_Y: out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); - FG_FETCH: out std_logic); + BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + FG_FETCH : out std_logic); end component; component ppu_sprite_bg port( -- background sprite -- inputs - CLK: in std_logic; -- system clock - RESET: in std_logic; -- reset clock counter - OE: in std_logic; -- output enable (of CIDX) - X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x - Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + CLK : in std_logic; -- system clock + RESET : in std_logic; -- reset clock counter + OE : in std_logic; -- output enable (of CIDX) + X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y -- aux inputs - BG_SHIFT_X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); - BG_SHIFT_Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + BG_SHIFT_X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + BG_SHIFT_Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- used memory blocks - BAM_ADDR: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - BAM_DATA: in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); - TMM_ADDR: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - TMM_DATA: in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); + BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + BAM_DATA : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); + TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); -- outputs - CIDX: out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color + CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color end component; component ppu_sprite_fg port( -- foreground sprite -- inputs - CLK: in std_logic; -- system clock - RESET: in std_logic; -- reset internal memory and clock counters - OE: in std_logic; -- output enable (of CIDX) - X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x - Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y - FETCH: in std_logic; -- fetch sprite data from TMM (TODO: generic map, set foreground sprite component index) + CLK : in std_logic; -- system clock + RESET : in std_logic; -- reset internal memory and clock counters + OE : in std_logic; -- output enable (of CIDX) + X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index) -- internal memory block (FAM) - FAM_WEN: in std_logic; -- VRAM FAM write enable - FAM_ADDR: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address - FAM_DATA: in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data + FAM_WEN : in std_logic; -- VRAM FAM write enable + FAM_ADDR : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address + FAM_DATA : in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data -- used memory blocks - TMM_ADDR: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - TMM_DATA: in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); + TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); -- outputs - CIDX: out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color - HIT: out std_logic); -- current pixel is not transparent + CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color + HIT : out std_logic); -- current pixel is not transparent end component; component ppu_comp port( -- compositor - FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); - BG_EN: out std_logic; - FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0)); + FG_HIT : in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + BG_EN : out std_logic; + FG_EN : out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0)); end component; component ppu_plut port( -- palette lookup table - CLK: in std_logic; -- system clock - CIDX: in std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- color in - RESET: in std_logic; + CLK : in std_logic; -- system clock + CIDX : in std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- color in + RESET : in std_logic; -- internal memory block (AUX) - PAL_WEN: in std_logic; -- VRAM PAL write enable - PAL_ADDR: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- VRAM PAL address - PAL_DATA: in std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); -- VRAM PAL data + PAL_WEN : in std_logic; -- VRAM PAL write enable + PAL_ADDR : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- VRAM PAL address + PAL_DATA : in std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); -- VRAM PAL data - R,G,B: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out + R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out end component; component ppu_vga_tiny port( -- tiny vga signal generator - CLK: in std_logic; -- system clock - RESET: in std_logic; + CLK : in std_logic; -- system clock + RESET : in std_logic; - X: out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x - Y: out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y VSYNC, VBLANK, - HSYNC, HBLANK: out std_logic); -- VGA sync outputs + HSYNC, HBLANK : out std_logic); -- VGA sync outputs end component; component ppu_vga_native port( -- native vga signal generator (upscaler) - CLK: in std_logic; -- system clock - RESET: in std_logic; + CLK : in std_logic; -- system clock + RESET : in std_logic; - X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x - Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y - PREADY: in std_logic; -- current pixel ready (pixel color is stable) - RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in + X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + PREADY : in std_logic; -- current pixel ready (pixel color is stable) + RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in - RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out - VSYNC, HSYNC: out std_logic); -- VGA sync outputs + RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out + VSYNC, HSYNC : out std_logic); -- VGA sync outputs end component; -- signals - signal SYSCLK, SYSRST: std_logic; -- system clock and reset - signal PL_SPRITE, PL_COMP_PAL, PL_DONE: std_logic; -- pipeline stages - signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN: std_logic; - signal TMM_AI, TMM_AO: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - signal BAM_AI, BAM_AO: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - signal FAM_AI, FAM_AO: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - signal PAL_AI, PAL_AO: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - signal AUX_AI, AUX_AO: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - signal TMM_DO: std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); - signal BAM_DO: std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); - signal FAM_DO: std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); - signal PAL_DO: std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); - signal AUX_DO: std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); - signal CIDX: std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); - signal BG_EN: std_logic; - signal FG_EN, FG_HIT: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); - signal X: std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x - signal Y: std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y - signal UR,UG,UB: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- unstable RGB (to be buffered) - signal SR,SG,SB: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- stable RGB (buffered until PL_COMP_PAL) - signal BG_SHIFT_X: std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); - signal BG_SHIFT_Y: std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); - signal FG_FETCH: std_logic; + signal SYSCLK, SYSRST : std_logic; -- system clock and reset + signal PL_SPRITE, PL_COMP_PAL, PL_DONE : std_logic; -- pipeline stages + signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic; + signal TMM_AI, TMM_AO : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + signal BAM_AI, BAM_AO : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + signal FAM_AI, FAM_AO : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + signal PAL_AI, PAL_AO : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + signal AUX_AI, AUX_AO : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + signal TMM_DO : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); + signal BAM_DO : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); + signal FAM_DO : std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); + signal PAL_DO : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); + signal AUX_DO : std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); + signal CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); + signal BG_EN : std_logic; + signal FG_EN, FG_HIT : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + signal UR,UG,UB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- unstable RGB (to be buffered) + signal SR,SG,SB : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- stable RGB (buffered until PL_COMP_PAL) + signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + signal FG_FETCH : std_logic; begin SYSCLK <= CLK100; SYSRST <= RESET; @@ -197,14 +197,14 @@ begin FAM_AI <= (others => '0'); PAL_AI <= (others => '0'); - pipeline_clock_edge_generator: component ppu_pceg port map( + pipeline_clock_edge_generator : component ppu_pceg port map( CLK => SYSCLK, RESET => SYSRST, SPRITE => PL_SPRITE, COMP_PAL => PL_COMP_PAL, DONE => PL_DONE); - address_decoder: component ppu_addr_dec port map( + address_decoder : component ppu_addr_dec port map( EN => EN, WEN => WEN, ADDR => ADDR, @@ -224,7 +224,7 @@ begin PAL_WEN => PAL_WEN, AUX_WEN => AUX_WEN); - background_attribute_memory: component ppu_bam port map( + background_attribute_memory : component ppu_bam port map( clka => SYSCLK, rsta => SYSRST, wea => (others => BAM_WEN), @@ -232,7 +232,7 @@ begin dina => DATA(PPU_BAM_DATA_WIDTH-1 downto 0), douta => BAM_DO, rsta_busy => open); - tilemap_memory: component ppu_tmm port map( + tilemap_memory : component ppu_tmm port map( clka => SYSCLK, rsta => SYSRST, wea => (others => TMM_WEN), @@ -241,7 +241,7 @@ begin douta => TMM_DO, rsta_busy => open); - aux: component ppu_aux port map( + aux : component ppu_aux port map( CLK => SYSCLK, RESET => SYSRST, AUX_WEN => AUX_WEN, @@ -251,7 +251,7 @@ begin BG_SHIFT_Y => BG_SHIFT_Y, FG_FETCH => FG_FETCH); - background_sprite: component ppu_sprite_bg port map( + background_sprite : component ppu_sprite_bg port map( CLK => PL_SPRITE, RESET => SYSRST, OE => BG_EN, @@ -265,8 +265,8 @@ begin TMM_DATA => TMM_DO, CIDX => CIDX); - foreground_sprites: for FG_IDX in 0 to PPU_FG_SPRITE_COUNT-1 generate - foreground_sprite: component ppu_sprite_fg port map( + foreground_sprites : for FG_IDX in 0 to PPU_FG_SPRITE_COUNT-1 generate + foreground_sprite : component ppu_sprite_fg port map( CLK => PL_SPRITE, RESET => SYSRST, OE => FG_EN(FG_IDX), @@ -282,12 +282,12 @@ begin HIT => FG_HIT(FG_IDX)); end generate; - compositor: component ppu_comp port map( -- compositor + compositor : component ppu_comp port map( -- compositor FG_HIT => FG_HIT, BG_EN => BG_EN, FG_EN => FG_EN); - palette_lookup: component ppu_plut port map( -- palette lookup table + palette_lookup : component ppu_plut port map( -- palette lookup table CLK => SYSCLK, CIDX => CIDX, RESET => SYSRST, @@ -312,7 +312,7 @@ begin end if; end process; - tiny_vga_signal_generator: component ppu_vga_tiny port map( -- tiny vga signal generator + tiny_vga_signal_generator : component ppu_vga_tiny port map( -- tiny vga signal generator CLK => SYSCLK, RESET => SYSRST, X => X, @@ -322,7 +322,7 @@ begin HSYNC => THSYNC, HBLANK => THBLANK); - native_vga_signal_generator: component ppu_vga_native port map( -- native vga signal generator (upscaler) + native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler) CLK => SYSCLK, RESET => SYSRST, X => X, diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhd b/basys3/basys3.srcs/ppu_addr_dec.vhd index 28c22fc..df83964 100644 --- a/basys3/basys3.srcs/ppu_addr_dec.vhd +++ b/basys3/basys3.srcs/ppu_addr_dec.vhd @@ -5,28 +5,28 @@ use ieee.std_logic_1164.all; use work.ppu_consts.all; entity ppu_addr_dec is port( - EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) - WEN: in std_logic; -- EXT write enable + EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) + WEN : in std_logic; -- EXT write enable TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, - AUX_WEN: out std_logic; -- write enable MUX - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in - TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); + AUX_WEN : out std_logic; -- write enable MUX + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in + TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); end ppu_addr_dec; architecture Behavioral of ppu_addr_dec is - signal TMM_RANGE, BAM_RANGE, FAM_RANGE, PAL_RANGE, AUX_RANGE: std_logic := '0'; -- ADDR in range of memory area + signal TMM_RANGE, BAM_RANGE, FAM_RANGE, PAL_RANGE, AUX_RANGE : std_logic := '0'; -- ADDR in range of memory area begin -- address MUX TMM_AO <= ADDR(PPU_TMM_ADDR_WIDTH-1 downto 0) when EN = '1' else TMM_AI; diff --git a/basys3/basys3.srcs/ppu_addr_dec_tb.vhd b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd index 5c7119d..f31ee67 100644 --- a/basys3/basys3.srcs/ppu_addr_dec_tb.vhd +++ b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd @@ -12,41 +12,41 @@ end ppu_addr_dec_tb; architecture behavioral of ppu_addr_dec_tb is component ppu_addr_dec port( - EN: in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) - WEN: in std_logic; -- EXT write enable + EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI) + WEN : in std_logic; -- EXT write enable TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, - AUX_WEN: out std_logic; -- write enable MUX - ADDR: in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in - TMM_AI: in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AI: in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AI: in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AI: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AI: in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - TMM_AO: out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - BAM_AO: out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - FAM_AO: out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - PAL_AO: out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - AUX_AO: out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); + AUX_WEN : out std_logic; -- write enable MUX + ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in + TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0)); end component; - signal EN: std_logic; - signal WEN: std_logic; - signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN: std_logic; - signal ADDR: std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); - signal TMM_AI: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - signal BAM_AI: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - signal FAM_AI: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - signal PAL_AI: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - signal AUX_AI: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); - signal TMM_AO: std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); - signal BAM_AO: std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); - signal FAM_AO: std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); - signal PAL_AO: std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); - signal AUX_AO: std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + signal EN : std_logic; + signal WEN : std_logic; + signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic; + signal ADDR : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); + signal TMM_AI : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + signal BAM_AI : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + signal FAM_AI : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + signal PAL_AI : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + signal AUX_AI : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); + signal TMM_AO : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); + signal BAM_AO : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); + signal FAM_AO : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); + signal PAL_AO : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); + signal AUX_AO : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); begin - uut: ppu_addr_dec port map( + uut : ppu_addr_dec port map( EN => EN, WEN => WEN, TMM_WEN => TMM_WEN, @@ -75,7 +75,7 @@ begin PAL_AI <= (others => '0'); AUX_AI <= (others => '0'); - tb: process + tb : process begin for i in 0 to 65535 loop ADDR <= std_logic_vector(to_unsigned(i,16)); diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd index c063586..3e7d46d 100644 --- a/basys3/basys3.srcs/ppu_consts.vhd +++ b/basys3/basys3.srcs/ppu_consts.vhd @@ -1,22 +1,22 @@ package ppu_consts is - constant PPU_RAM_BUS_ADDR_WIDTH: natural := 16; -- RAM bus address width - constant PPU_RAM_BUS_DATA_WIDTH: natural := 16; -- RAM bus data width - constant PPU_FG_SPRITE_COUNT: natural := 128; -- amount of foreground sprites - constant PPU_COLOR_OUTPUT_DEPTH: natural := 4; -- VGA output channel depth - constant PPU_PALETTE_IDX_WIDTH: natural := 3; -- palette index width (within sprite) - constant PPU_PALETTE_WIDTH: natural := 3; -- palette index width (palette table) - constant PPU_PALETTE_CIDX_WIDTH: natural := PPU_PALETTE_IDX_WIDTH + PPU_PALETTE_WIDTH; -- global palette index width - constant PPU_TMM_ADDR_WIDTH: natural := 16; - constant PPU_TMM_DATA_WIDTH: natural := 16; - constant PPU_BAM_ADDR_WIDTH: natural := 11; - constant PPU_BAM_DATA_WIDTH: natural := 15; - constant PPU_FAM_ADDR_WIDTH: natural := 8; - constant PPU_FAM_DATA_WIDTH: natural := 16; - constant PPU_PAL_ADDR_WIDTH: natural := 6; - constant PPU_PAL_DATA_WIDTH: natural := 12; - constant PPU_AUX_ADDR_WIDTH: natural := 2; - constant PPU_AUX_DATA_WIDTH: natural := 16; - constant PPU_POS_H_WIDTH: natural := 9; -- amount of bits for horizontal screen offset - constant PPU_POS_V_WIDTH: natural := 8; -- amount of bits for vertical screen offset + constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width + constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width + constant PPU_FG_SPRITE_COUNT : natural := 128; -- amount of foreground sprites + constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth + constant PPU_PALETTE_IDX_WIDTH : natural := 3; -- palette index width (within sprite) + constant PPU_PALETTE_WIDTH : natural := 3; -- palette index width (palette table) + constant PPU_PALETTE_CIDX_WIDTH : natural := PPU_PALETTE_IDX_WIDTH + PPU_PALETTE_WIDTH; -- global palette index width + constant PPU_TMM_ADDR_WIDTH : natural := 16; + constant PPU_TMM_DATA_WIDTH : natural := 16; + constant PPU_BAM_ADDR_WIDTH : natural := 11; + constant PPU_BAM_DATA_WIDTH : natural := 15; + constant PPU_FAM_ADDR_WIDTH : natural := 8; + constant PPU_FAM_DATA_WIDTH : natural := 16; + constant PPU_PAL_ADDR_WIDTH : natural := 6; + constant PPU_PAL_DATA_WIDTH : natural := 12; + constant PPU_AUX_ADDR_WIDTH : natural := 2; + constant PPU_AUX_DATA_WIDTH : natural := 16; + constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset + constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset end package ppu_consts; diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd index 9675e5b..1aaeee4 100644 --- a/basys3/basys3.srcs/ppu_pceg.vhd +++ b/basys3/basys3.srcs/ppu_pceg.vhd @@ -3,18 +3,18 @@ use ieee.std_logic_1164.all; --use ieee.numeric_std.all; entity ppu_pceg is port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done + CLK : in std_logic; -- system clock + RESET : in std_logic; -- async reset + SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch + COMP_PAL : out std_logic; -- compositor + palette lookup + DONE : out std_logic); -- last pipeline stage done end ppu_pceg; architecture Behavioral of ppu_pceg is - constant PPU_PL_TOTAL_STAGES: natural := 14; + constant PPU_PL_TOTAL_STAGES : natural := 14; type states is (PL_SPRITE, PL_COMP_PAL, PL_DONE); - signal state: states := PL_SPRITE; + signal state : states := PL_SPRITE; begin -- output drivers SPRITE <= CLK when RESET = '0' and state = PL_SPRITE else '0'; @@ -22,7 +22,7 @@ begin DONE <= '1' when RESET = '0' and state = PL_DONE else '0'; process(CLK, RESET) - variable CLK_IDX: natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0; + variable CLK_IDX : natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0; begin if RESET = '1' then state <= PL_SPRITE; diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhd b/basys3/basys3.srcs/ppu_pceg_tb.vhd index 137d4b4..719ec06 100644 --- a/basys3/basys3.srcs/ppu_pceg_tb.vhd +++ b/basys3/basys3.srcs/ppu_pceg_tb.vhd @@ -10,27 +10,27 @@ end ppu_pceg_tb; architecture behavioral of ppu_pceg_tb is component ppu_pceg port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done + CLK : in std_logic; -- system clock + RESET : in std_logic; -- async reset + SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch + COMP_PAL : out std_logic; -- compositor + palette lookup + DONE : out std_logic); -- last pipeline stage done end component; - signal CLK: std_logic := '0'; - signal RESET: std_logic := '0'; - signal SPRITE: std_logic; - signal COMP_PAL: std_logic; - signal DONE: std_logic; + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + signal SPRITE : std_logic; + signal COMP_PAL : std_logic; + signal DONE : std_logic; begin - uut: ppu_pceg port map( + uut : ppu_pceg port map( CLK => CLK, RESET => RESET, SPRITE => SPRITE, COMP_PAL => COMP_PAL, DONE => DONE); - tb: process + tb : process begin for i in 0 to 32 loop if i > 20 then @@ -51,4 +51,5 @@ before formatting as a failsafe. - testbench name is the component name with `_tb` as suffix - vhdl filename is the same as the component name - vhdl files should end in the `.vhd` file extension, not `.vhdl` +- use spaces around the colon used for setting the type of signal definitions |