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-rw-r--r--basys3/basys3.srcs/apu.vhd46
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency.vhd57
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency_tb.vhd33
-rw-r--r--basys3/basys3.srcs/apu_tb_note_to_frequency.vhd40
-rw-r--r--basys3/basys3.srcs/ppu.vhd16
-rw-r--r--basys3/basys3.srcs/ppu_consts.vhd4
-rw-r--r--basys3/basys3.xpr24
-rw-r--r--style.md2
8 files changed, 116 insertions, 106 deletions
diff --git a/basys3/basys3.srcs/apu.vhd b/basys3/basys3.srcs/apu.vhd
index ea2a342..4a594ab 100644
--- a/basys3/basys3.srcs/apu.vhd
+++ b/basys3/basys3.srcs/apu.vhd
@@ -2,35 +2,31 @@ library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
-entity apu is
- port(
- CLK100: in std_logic; -- system clock
- RESET: in std_logic; -- global (async) system reset
- DATA: in std_logic_vector(15 downto 0);
- SOUND: out std_logic);
+entity apu is port(
+ CLK100: in std_logic; -- system clock
+ RESET: in std_logic; -- global (async) system reset
+ DATA: in std_logic_vector(15 downto 0);
+ SOUND: out std_logic);
- -- EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers)
- -- WEN: in std_logic; -- PPU VRAM write enable
- -- ADDR: in std_logic_vector(15 downto 0); -- PPU VRAM ADDR
- -- R,G,B: out std_logic_vector(3 downto 0);
- -- NVSYNC, NHSYNC: out std_logic; -- native VGA out
- -- TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out
+ -- EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers)
+ -- WEN: in std_logic; -- PPU VRAM write enable
+ -- ADDR: in std_logic_vector(15 downto 0); -- PPU VRAM ADDR
+ -- R,G,B: out std_logic_vector(3 downto 0);
+ -- NVSYNC, NHSYNC: out std_logic; -- native VGA out
+ -- TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out
end apu;
architecture Behavioral of apu is
-
- component apu_note_to_frequency port (
- data : in std_logic_vector(7 downto 0);
- freq : out std_logic_vector(7 downto 0) --frequency
- );
+ component apu_note_to_frequency port(
+ data: in std_logic_vector(7 downto 0);
+ freq: out std_logic_vector(7 downto 0)); --frequency
end component;
- component apu_LUT_reader port (
- clk : in std_logic;
- rst : in std_logic;
- wave : in std_logic_vector(1 downto 0);
- level : out std_logic_vector(7 downto 0)
- );
+ component apu_LUT_reader port(
+ clk: in std_logic;
+ rst: in std_logic;
+ wave: in std_logic_vector(1 downto 0);
+ level: out std_logic_vector(7 downto 0));
end component;
-
begin
-end architecture; \ No newline at end of file
+
+end architecture;
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 878da30..7e02c75 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -2,39 +2,34 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity apu_note_to_frequency is
- port (
- -- clk : in std_logic;
- -- rst : in std_logic;
- data : in std_logic_vector(7 downto 0);
- freq : out std_logic_vector(11 downto 0) --frequency
- );
+entity apu_note_to_frequency is port (
+ -- clk : in std_logic;
+ -- rst : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ freq : out std_logic_vector(11 downto 0)); --frequency
end entity;
architecture Behavioral of apu_note_to_frequency is
-signal buffSmall : std_logic_vector(7 downto 0) := (others => '0');
-signal buff : std_logic_vector(15 downto 0) := (others => '0');
-signal shift : integer;
+ signal buff_small: std_logic_vector(7 downto 0) := (others => '0');
+ signal buff: std_logic_vector(15 downto 0) := (others => '0');
+ signal shift: integer;
begin
+ shift <= to_integer(unsigned(data(2 downto 0)));
+ buff_small <=
+ x"f0" when data(7 downto 3) = (x"c" & '0') else -- C 496
+ x"d0" when data(7 downto 3) = (x"c" & '1') else -- C# 464
+ x"b0" when data(7 downto 3) = (x"d" & '0') else -- D 432
+ x"a0" when data(7 downto 3) = (x"d" & '1') else -- D# 416
+ x"80" when data(7 downto 3) = (x"e" & '0') else -- E 384
+ x"70" when data(7 downto 3) = (x"f" & '0') else -- F 368
+ x"58" when data(7 downto 3) = (x"f" & '1') else -- F# 344
+ x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320
+ x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304
+ x"20" when data(7 downto 3) = (x"a" & '0') else -- A 288
+ x"10" when data(7 downto 3) = (x"a" & '1') else -- A# 272
+ x"00" when data(7 downto 3) = (x"b" & '0') else -- B 256
+ x"01";
- shift <= to_integer(unsigned( data(2 downto 0) ));
-
- buffSmall <=
- x"F0" when data(7 downto 3) = (x"C" & '0') else -- C 496
- x"D0" when data(7 downto 3) = (x"C" & '1') else -- C# 464
- x"B0" when data(7 downto 3) = (x"D" & '0') else -- D 432
- x"A0" when data(7 downto 3) = (x"D" & '1') else -- D# 416
- x"80" when data(7 downto 3) = (x"E" & '0') else -- E 384
- x"70" when data(7 downto 3) = (x"F" & '0') else -- F 368
- x"58" when data(7 downto 3) = (x"F" & '1') else -- F# 344
- x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320
- x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304
- x"20" when data(7 downto 3) = (x"A" & '0') else -- A 288
- x"10" when data(7 downto 3) = (x"A" & '1') else -- A# 272
- x"00" when data(7 downto 3) = (x"B" & '0') else -- B 256
- x"01";
-
- buff <= x"1" & buffSmall;
- freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2)
-
-end architecture; \ No newline at end of file
+ buff <= x"1" & buff_small;
+ freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2)
+end architecture;
diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
new file mode 100644
index 0000000..6814c1f
--- /dev/null
+++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity apu_note_to_frequency_tb is
+end entity;
+
+architecture Behavioral of apu_note_to_frequency_tb is
+ component apu_note_to_frequency is port(
+ data: in std_logic_vector(7 downto 0);
+ freq: out std_logic_vector(11 downto 0)); -- frequency
+ end component;
+
+ signal data: std_logic_vector(7 downto 0) := (others => '0');
+ signal freq: std_logic_vector(11 downto 0) := (others => '0');
+
+ signal ok: boolean := false;
+begin
+ uut: apu_note_to_frequency port map(
+ data => data,
+ freq => freq);
+
+ tb: process
+ begin
+ for i in 0 to 255 loop
+ data <= std_logic_vector(to_unsigned(i, 8));
+ wait for 4 ps;
+ end loop;
+ end process;
+end architecture;
diff --git a/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd b/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd
deleted file mode 100644
index 385071e..0000000
--- a/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd
+++ /dev/null
@@ -1,40 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity apu_tb_note_to_frequency is
-end entity;
-
-architecture Behavioral of apu_tb_note_to_frequency is
-
- component apu_note_to_frequency is
- port (
- data : in std_logic_vector(7 downto 0);
- freq : out std_logic_vector(11 downto 0) --frequency
- );
- end component;
-
- signal data : std_logic_vector(7 downto 0) := (others => '0');
- signal freq : std_logic_vector(11 downto 0) := (others => '0');
-
- signal OK : boolean := false;
-
-begin
- UUT: apu_note_to_frequency
- port map (
- data => data,
- freq => freq
- );
-
- TB: process
- begin
- for I in 0 to 255 loop
- data <= std_logic_vector(to_unsigned(I, 8));
- wait for 4 ps;
- end loop;
- end process;
-
-end architecture; \ No newline at end of file
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 28134c6..663f3ab 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -188,14 +188,14 @@ begin
SYSCLK <= CLK100;
SYSRST <= RESET;
- -- internal unused lines
- --
- -- these lines would be used if components use memory blocks as RAM blocks
- -- (like how TMM and BAM work), the registers of these memory regions are
- -- directly exposed internally, and are as such not used as RAM blocks
- AUX_AI <= (others => '0');
- FAM_AI <= (others => '0');
- PAL_AI <= (others => '0');
+ -- internal unused lines
+ --
+ -- these lines would be used if components use memory blocks as RAM blocks
+ -- (like how TMM and BAM work), the registers of these memory regions are
+ -- directly exposed internally, and are as such not used as RAM blocks
+ AUX_AI <= (others => '0');
+ FAM_AI <= (others => '0');
+ PAL_AI <= (others => '0');
pipeline_clock_edge_generator: component ppu_pceg port map(
CLK => SYSCLK,
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index d3c8403..c063586 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -1,6 +1,6 @@
package ppu_consts is
- constant PPU_RAM_BUS_ADDR_WIDTH: natural := 16; -- RAM bus address width
- constant PPU_RAM_BUS_DATA_WIDTH: natural := 16; -- RAM bus data width
+ constant PPU_RAM_BUS_ADDR_WIDTH: natural := 16; -- RAM bus address width
+ constant PPU_RAM_BUS_DATA_WIDTH: natural := 16; -- RAM bus data width
constant PPU_FG_SPRITE_COUNT: natural := 128; -- amount of foreground sprites
constant PPU_COLOR_OUTPUT_DEPTH: natural := 4; -- VGA output channel depth
constant PPU_PALETTE_IDX_WIDTH: natural := 3; -- palette index width (within sprite)
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 5df2675..466cc1f 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -114,6 +114,22 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/apu.vhd">
+ <FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/apu_note_to_frequency.vhd">
+ <FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ppu"/>
@@ -141,6 +157,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/apu_note_to_frequency_tb.vhd">
+ <FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ppu_addr_dec_tb"/>
diff --git a/style.md b/style.md
index 3347e60..7e6b9b6 100644
--- a/style.md
+++ b/style.md
@@ -48,4 +48,6 @@ before formatting as a failsafe.
- use snake case for naming components
- use uppercase snake case for naming signals and I/O lines
- use lower case keywords
+- testbench name is the component name with `_tb` as suffix
+- vhdl filename is the same as the component name