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authorUnavailableDev <ggwildplay@gmail.com>2023-03-11 09:07:35 +0100
committerUnavailableDev <ggwildplay@gmail.com>2023-03-11 09:07:35 +0100
commit33fa63ee205892205d9cd229c363f7c28d99e636 (patch)
treec7c1323e36182840d5021f9ed38727e4dfaca208 /pinout.md
parentadde3c22fa09092d238b165b2a65e5bfa48f00ea (diff)
parent877ac831461f35d00e0e0ab7d6afbe93768fc7c6 (diff)
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-Pin layout
-
-| pin STM | function |
-|---------|----------|
-| PA5 / D13 | SPI clock |
-| PA7 / D11 | SPI MOSI |
-| PA9 / D8 | SPI cs |
-| PB4 / D5 | button 1 |
-| PB5 / D4 | button 2 |
-| PB6 / D10 | button 3 |
-| PB8 / D15 | button 4 |
-
-| pin FPGA | function |
-|---------|----------|
-| JB 7 | SPI clock |
-| JB 8 | SPI data |
-| JB 9 | SPI cs |
-
-
-
-constraints:
-
-set_property PACKAGE_PIN A15 [get_ports clkSPI]
-
-set_property PACKAGE_PIN C15 [get_ports csSPI]
-
-set_property PACKAGE_PIN A17 [get_ports dataSPI]
-
-set_property IOSTANDARD LVCMOS33 [get_ports dataSPI]
-
-set_property IOSTANDARD LVCMOS33 [get_ports csSPI]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clkSPI] .