move architecture from research into architecture.md and update ppu design files

3 files changed, 214 insertions, 205 deletions

diff --git a/docs/architecture.md b/docs/architecture.md
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+# General system architecture
+
+<!-- TODO: top-level system architecture + context diagram -->
+
+## PPU
+
+Here's a list of features our PPU has:
+
+- 320x240 @ 60Hz VGA output (upscaled to 640x480)
+- single tilemap with room for 1024 tiles of 16x16 pixels
+- 8 colors per palette, with 4096 possible colors (12-bit color depth)
+- 640x480 background canvas with scrolling
+- NO background scrolling splits
+- 128 total sprites on screen (NO scanline sprite limit)
+- sprites are always drawn on top of the background layer
+- PPU control using DMA (dual-port asynchronous RAM)
+- tiles can be flipped using FAM or BAM
+- no frame buffer
+- vertical and horizontal sync and blank output
+
+Notable differences:
+
+- NES nametable equivalent is called BAM (background attribute register)
+- NES OAM equivalent is called FAM (foreground attribute register)
+- 320x240 @ 60Hz output
+  
+  Since we're using VGA, we can't use custom resolutions without an
+  upscaler/downscaler. This resolution was chosen because it's exactly half of
+  the lowest standard VGA resolution 640x480.
+- No scanline sprite limit  
+  
+  Unless not imposing any sprite limit makes the hardware implementation
+  impossible, or much more difficult, this is a restriction that will likely
+  lead to frustrating debugging sessions, so will not be replicated in our
+  custom PPU.
+- Sprites are 16x16
+  
+  Most NES games already tile multiple 8x8 tiles together into "metatiles" to
+  create the illusion of larger sprites. This was likely done to save on memory
+  costs as RAM was expensive in the '80s, but since we're running on an FPGA
+  cost is irrelevant.
+- Single 1024 sprite tilemap shared between foreground and background sprites
+  
+  The NES OAM registers contain a bit to select which tilemap to use (of two),
+  which effectively expands each tile's index address by one byte. Instead of
+  creating the illusion of two separate memory areas for tiles, having one
+  large tilemap seems like a more sensible solution to indexed tiles.
+- 8 total palettes, with 8 colors each
+  
+  More colors is better. Increasing the total palette count is a very memory
+  intensive operation, while increaing the palette color count is likely slower
+  when looking up color values for each pixel on real hardware.
+- Sprites can be positioned paritally off-screen on all screen edges using only
+  the offset bits in the FAM register
+  
+  The NES has a separate PPUMASK register to control special color effects, and
+  to shift sprites off the left and top screen edges, as the sprite offsets
+  count from 0. Our PPU's FAM sprite offset bits count from -15, so the sprite
+  can shift past the top and left screen edges, as well as the standard bottom
+  and right edges.
+- No status line register, only V-sync and H-sync outputs are supplied back to
+  CPU
+  
+  The NES status line register contains some handy lines, such as a buggy
+  status line for reaching the max sprite count per scanline, and a status line
+  for detecting collisions between background and foreground sprites. Our PPU
+  doesn't have a scanline limit, and all hitbox detection is done in software.
+  Software hacks involving swapping tiles during a screen draw cycle can still
+  be achieved by counting the V-sync and H-sync pulses using interrupts.
+- No background scrolling splits
+  
+  This feature allows only part of the background canvas to be scrolled, while
+  another portion stays still. This was used to draw HUD elements on the
+  background layer for displaying things like health bars or score counters.
+  Since we are working with a higher foreground sprite limit, we'll use regular
+  foreground sprites to display HUD elements.
+- Sprites are always drawn on top of the background layer
+  
+  Our game doesn't need this capability for any visual effects. Leaving this
+  feature out will lead to a simpler hardware design
+
+### Hardware design schematics
+
+#### Top (level 1)
+
+![PPU top-level design](../assets/ppu-level-1.svg)
+
+Important notes:
+
+- The STM32 can reset the PPU. This line will also be connected to a physical
+  button on the FPGA.
+- The STM32 uses direct memory access to control the PPU.
+- The PPU's native resolution is 320x240. It works in this resolution as if it
+  is a valid VGA signal. The STM32 is also only aware of this resolution. This
+  resolution is referred to as "tiny" resolution. Because VGA-compatible LCD's
+  likely don't support this resolution due to low clock speed, a built-in
+  pixel-perfect 2X upscaler is chained after the PPU's "tiny" output. This
+  means that the display sees the resolution as 640x480, but the PPU and STM32
+  only work in 320x240.
+- The STM32 receives the TVSYNC and THSYNC lines from the PPU. These are the
+  VSYNC and HSYNC lines from the tiny VGA signal generator. These lines can be
+  used to trigger interrupts for counting frames, and to make sure no
+  read/write conflicts occur for protected memory regions in the PPU.
+- NVSYNC, NHSYNC and the RGB signals refer to the output of the native VGA
+  signal generator.
+
+#### Level 2
+
+![PPU level 2 design (data flows from top to bottom)](../assets/ppu-level-2.svg)
+
+Important notes:
+
+- The pixel fetch logic is pipelined in 5 stages:
+  1. - (Foreground sprite info) calculate if foreground sprite exists at
+     current pixel using FAM register
+     - (Background sprite info) get background sprite info from BAM register
+  2. - (Sprite render) calculate pixel to read from TMM based on sprite info
+  3. - (Compositor) get pixel with 'highest' priority (pick first foreground
+     sprite with non-transparent color at current pixel in order, fallback to
+     background)
+     - (Palette lookup) lookup palette color using palette register
+     - (VGA signal generator) output real color to VGA signal generator
+- The pipeline stages with two clock cycles contain an address set and memory
+  read step.
+- The pipeline takes 5 clock ticks in total. About 18 are available during each
+  pixel. For optimal display compatibility, the output color signal should be
+  stable before 50% of the pixel clock pulse width (9 clock ticks).
+- Since the "sprite info" and "sprite render" steps are fundamentally different
+  for the foreground and background layer, these components will be combined
+  into one for each layer respectively. They are separated in the above diagram
+  for pipeline stage illustration.
+- The BAX, FAM, and PAL registers are implemented in the component that
+  directly accesses them, but are exposed to the PPU RAM bus for writing.
+- Each foreground sprite render component holds its own sprite data copy from
+  the RAM in it's own cache memory. The cache updates are fetched during the
+  VBLANK time between each frame.
+
+#### Level 3
+
+This diagram has several flaws, but a significant amount of time has already
+been spent on these, so they are highlighted here instead of being fixed.
+
+![PPU level 3 design](../assets/ppu-level-3.svg)
+
+Flaws:
+
+- Pipeline stages 1-4 aren't properly connected in this diagram, see level 2
+  notes for proper functionality
+- The global RESET input resets all PPU RAM, but isn't connected to all RAM
+  ports
+- All DATA inputs on the same line as an ADDR output are connections to a
+  memory component. Not all of these are connected in the diagram, though they
+  should be.
+- All ADDR and ADDR drivers are also tri-state. EN inputs need to be added to
+  support switching the output on/off.
+
+Important notes:
+
+- The background sprite and foreground sprite component internally share some
+  components for coordinate transformations
+- The foreground sprite component is only shown once here, but is cloned for
+  each foreground sprite the PPU allows.
+- The CIDX lines between the sprite and compositor components is shared by all
+  sprite components, and is such tri-state. A single sprite component outputs a
+  CIDX signal based on the \*EN signal from the compositor.
+- All DATA and ADDR lines are shared between all RAM ports. WEN inputs are
+  controlled by the address decoder.
+
+### Registers
+
+|Address|Size (bytes)|Alias|Description|
+|-|-|-|-|
+|`0x00000`|`0x00000`|TMM  |[tilemap memory][TMM]|
+|`0x00000`|`0x00000`|BAM  |[background attribute memory][BAM]|
+|`0x00000`|`0x00000`|FAM  |[foreground attribute memory][FAM]|
+|`0x00000`|`0x00000`|PAL  |[palettes][PAL]|
+|`0x00000`|`0x00000`|BAX  |[background auxiliary memory][BAX]|
+
+[TMM]: #tilemap-memory
+#### Tilemap memory
+
+- TODO: list format
+
+[BAM]: #background-attribute-memory
+#### Background attribute memory
+
+- TODO: list format
+
+[FAM]: #foreground-attribute-memory
+#### Foreground attribute memory
+
+- TODO: list format
+
+[PAL]: #palettes
+#### Palettes
+
+- TODO: list format
+
+[BAX]: #background-auxiliary-memory
+#### Background auxiliary memory
+
+- background scrolling
+
+[nesppuspecs]: https://www.copetti.org/writings/consoles/nes/
+[nesppudocs]: https://www.nesdev.org/wiki/PPU_programmer_reference
+[nesppupinout]: https://www.nesdev.org/wiki/PPU_pinout
+[custompputimings]: https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
+
diff --git a/docs/ppu.drawio b/docs/ppu.drawio
index a9e20e8..18970be 100644
--- a/docs/ppu.drawio
+++ b/docs/ppu.drawio
@@ -1 +1 @@
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id="lj51MlK96fuJFRP7cw84" name="level-3">7V1bV+q6Fv41a4xzHtiD3uERAdF1vIKuvXxygFRFC2XVurz8+lOkRUgmSUuTNKR92GMvagJtvq8z854fRnv63guG88dTf+x6P/T6+P2H0fmh63q9YUb/W1z5WF5xms3lhYdgMl5e0r4vDCafbnyxHl99nYzdl42Boe974WS+efHOn83cu3Dj2jAI/LfNYfe+t/mr8+GDi10Y3A09/Oq/k3H4uLzasOrf14/cycNj8staPf7LdJgMji+8PA7H/tvaJaP7w2gHvh8u/zV9b7veYvGSdVnOO9zy19WNBe4sTDPhrdsyOkdvVv/k8ul4cP3ZHR3/rtnxvYUfyQO74+j5449+ED76D/5s6HW/rx4E/uts7C6+tR59+h5z4vvz6KIWXXxyw/AjBnP4GvrRpcdw6sV/jW44+Pgdz//6cLP+ofO+8ekj/oQ/b7wEL/5rcBffffe02fHMl+PTp9F0dH171mreNmtOzJth8ODGU0dP7dfH69Hhb/1v4+bPS8e3D5yaZi0HLpZg7Rfi5ey5/tSNbigaELjeMJz83aTIMGbaw2rcauqFP4nuWa8nb0XCnvidMJLPyVcs7zSe9Q1pKwiGH2vD5osBL4TfqSO/07Q2GUIZrzl14viaaeScoG9OiP6xfMbk09qqf1/64nUGjjtl4LidluOmII6bYjiuNZHfaZA5jo7XGjTK6jkn6LYAjmsJT5Qmud7AWQ4O5MTy7eRcQ5cNnnop8GymxZPPziwQT6MMeCa7Ox1Pe8/xNONb+Tv0XuObwwB+iPCbb13Mv24Quu8bl2IbZjhKvqEOL0qy0zSQnSbZYt++DZVkF35cs1GM+vZl3FinrItiNLBFicyh06NPbGk2mf32OAndwXz4xa23yI7cZPFL9JfJ7OHEvV88QM2qf1/rx0+1vOgNR6534b9Mwok/i67eRWvuBtEfFms9iWy6E2TAyA9DfxoNGHqTB3BGK/5DuHjjkl/d+p6QqYICjgNbFHDJj60B1z75H4ZadPshAk0Y+M9u2/f8aNE6M3+2EFv3E89DLiXrGywfBlve6WQ8/hJ5EBU2ybKJAcIDnQss75uQJIoggFDzH8Ox8oP00Dh9vbn80/94uvrzPJid9axfFzVDAomjb1Hq14jbAJZF0xgwtz8fnbU/frq3/uNT7/Tnz6B+/7nSk9ZW5WLoRZuiG130fP85WY9dhQ9REAgVSTThQyRNJtnDDUJYF2gKEj7eF1rcZE8d4wUsjXLiFL96DQAiXgjpwPZw3PldQUSGyIBeI15beGLx7rA9ZHra9HtG4vDnpMjATMW3g3+7Z+oSlUwFOlPFiA9cc2l1Ov0KFYr8gBRMfiDh8qPTumpVIFFA0oUKeVxVKljIv29qjIgjQozMx70OPGSLRKbrigayCHiclr0KgQKFuYEr7AcVIGIENyhocbW03x10r9TdXdlYUNA+wg0jrYHBsd8hmqt7u/Vcm18dtO+sT+3zrX9peStbnhqiSVQL3okCNWdTd1iFzxknCtRQ9y0lGQYdb+oWQrF8YXxYTuCCO62Cx87J66ArldLL6zB4M5vnncNfs2vd+N/ANI/G3ealY9bwWFtrPA7clwjt+ti988dugK2SohEmMmtye3lZQAgL192jF9keObN/ClLMUBG0yzKA0jeJe5fFP0XmgnjzBbwfHBO13VN5QeFs0cC3x9jzwUB+wK4PaFXQ1Edm4kTHd8aDFo+4TDGWHpkJqYkKpVKwICpRv14PSLdOKkjEhMbgTReXHYet0woSMf4QGBLcZ3tQQSJqh4UhcTBIrk4rSIRqooZqpSrEbMN1FxSspDHP+s6FDpAlmVYHZeicQWq0BPpmYIxww/5iMne9yWyRgXfn+XfPCYJ6/cGducEw9MvtrjG32R7yuGsMa2eqZ3tkWc0tmOu41jKw1N4hV0Qo3NqCEcFV+4FZISLG2IJvD98kB3jtU8kRERp7NnAn0QCX5iVHRKgz09BxRPD63bIiIgYCxv5kBgoO53gU0cIqd+2FZF4AHQ9IlTJbSBp/GXh7zu4ShJ03AOt+kViEa4ajBmob3CrycPK2/el8YWKX3Ox30vNZCHpwLBwvA+BU6iWRcpIBmXcElUIkD+5yO+hxySJRCiOhZrADKFblK5nMABrnF6npXpy/WvrluDe/mL//8m4bh7U8Dv1sj5vZCAC8+uBGwM3V6ey+NOSl3n1phDy3hUdBD3v1+tFx2bRvZxtgBRlFFu57j4DRKmAkM4ts6AVyWhVOdJyEKig2/j79J/pYi/777/4htdhfhGIl1INvAwlsvUa1KaXASWg00tm9KRwvpQm1hYQoUTauPC72AOVN1PQdxQqR+Dg7FxpUhUqx+pIOGhwVKoJrgHB/DU91SAQSiLvczOKqzvzOiNWH8BjDQh+q3plCtZ+Gai3IiQESev18vM7ik5dhXXKPTvpYvqPJcStaWrzA514dGkNLNk88f7LgtUelACzxSkoyqHg5olvCx9+MtolYCdSVzKX0lUAnICdW5G4sAdNpj5qb7Egnonq9Tid4gXQ56GQjbNIpbELGW9TTScycE1j3QYHRkCG5xkJqDdJ2u2bSBwVaFQv3q1xNPHca6Zx6fepO/fg3StDsmswaKQprYAiBXjZKN5vICxRnSwYGCffJcOqFWox1mReT9E0/+UGE50Cp3a6W0XskFiQ8mVDpbkeMMOIVFYAxKlkFACOMhOapAUlJxWvDIivP4VUBeogM754fvkiz+MEwDCaj16+TYCrl+JtEEivHuNVXQuU4A1BFKMdAcF995TgDJhIox0Ckv4TKcfb3SCxIuJFZPuU4O0ZClWMbtzLLpxxnx4iXcgweaK7vUWBzq36+HscAnxKIOu9VVCxJECksKgZzR4YzNU2ko5fRxA0rzYZeKZuX3MO3pkM/cFeW1cs8mCzMqjzWVGq7CTa7BFpTZOZkK+YVC2PJdq+8QBXh2oEOP1Wp3jovJslfkTC3UIx0oKSpe9U+qt4k2hm1IlECGo9t2cvxjcZhIfl36PQDrA+LY/Lg9cGdApG9WePTCZt3uZeTy6JZUUV88jl8P7i+tfB7VtjIt18bcNy5gqrQKgH49nbPIeMt+M20Fh63tcEj818SZ387viP25JYdnUyU7OqoGLDwcpcvmcMHLMllTnG9+uDMgd1LfjkLGSiYwaKPJGwi4fJE4V5HZCZIwkygtedNBYlMuqS5u/eZs+wwitZPgIPN+HS7kCjHwNzdKyaGrriVet4tm0Qp7uhK+JXfo7IufInTFnElDS/Xo5/gciTHihUd/Ux0r7Qlgcj45L1OXZOVeUKSMsY3uipDERcaXdVjLMSE5eB1wZZlI2+1iq5+M0eS6Cp4k1V0NRNQReQGKd7MOi8kgoOr4O3ivq0te0TOqN22VclsG0FBTRZBO/C28cjzImbH54xnaRx/RJ5IonjjtSdf/vMKGdm2AFwH/fKdV0ClAIpXuA623VLnb4iW+KvmmSLcYfDawF0Davt7Zna6cB2ZKMX7yeD7w+27WOQoHa7Li5UYbFi73JkJGV7hOngZShWuIzNBFmaWKlyXF5IiNEkN1/lVjn8w8vfwqteDb09eHVJkyhf8LFt0SNVTvshEkVSHTHhbspSvvFgJwSZJpFcm5kps80CPucZULTrmaiZtSVYbDyXoik0wBMREk1R/tcmTNNCjkkeXhTzIObrUiD06IekNypc8RlnJQ8yL3nvyWIaAWndDpobi/1gs6HN1b7eea/Org/ad9al9vvUvLa+mOSnpk3hciqaPjXQ+0Gxay+ciWiUYqmWaweRppCSPLcnGZaMHUTs08iATdCHkaZaBPNBRE6SoftHcMZG0Q526b6ETmgKUnsRxogx3iB55quBJKm0KJw8qR6gpqMgE0xQgeEzVbHVi7IBOHkm6Q5kGQh6HRh5kgmmJII9q5has8jRTkifxexVNHhtNfm/QVB70BJOmCPLIZG7x8xIClRnENuOFkwctB6AaW2h3NlsEeVQztojtnunkkUXyoDpPM6OxZQiRPKoZW8Qex3TyGJKQx8gYn0AnIG5FPuSxVLO2iAKFrvNI6uYxskoeSwh5VLO2iAKFTh5JJQ81PoFOsDQR5NHLQJ5EoFB9hJJUMqMuPyurj9CoC/ARWqpZ6kR5QuVOUxLuoGeTajTuIBMMTQR3TMW489ZtGZ2jN6t/cvl0PLj+7I6Of68yGde5A7uDmAfVcyVbJX4DtdFJ9ltqe3/JwFHNx0Vac7qhKYnYddByblpIGJ2gi/BSWKp5KeAXO62haUvi4nKcjM51dIIhwtC0VTM0YfKkPfRFlyQRDpM8ZkbJ44jgjmr6HkiJ1HYmHx8F0OIKCcKhh0gubzSe9c2B7EYHcvAeLb6DjkcOKuLEQdXOrII5mDYfShgHEb9WQxAHaQpYMRwshfIOWVbFchBxzMf6FXcO0vS4YjioWpwbVs8A30uxHEQSyJuCOEgLWhXDQdUMUZiDQGJ797TZ8cyX49On0XR0fXvWat42V+lg3EmINubU6pxYiHW3o2b8bIw34hwnriRMtGFlSAgbtKlJKEnk1NGzGRPo+M0uu9j4Rp7RQqp+HNUcLaR9lx7Ql4OVlG2SPkFIJpGjK0YdUKSZgH1BzJQtmjycRRqWL5t1vC4iv9ZRLaqYOlEJ3G5lqSnKn6jUpEnCfOOF1Cw5qjkHU6dgwuSURHCiVST0FExkgl2nkM3KN94U0UXAUc1rmDPyJgc3ETFIjbsVkVnuJL3UijwNpIHWjgEnXUGNvtBo1S4pNHBeFt7h/Xg2f12iLeD8D4YnfcBHiex0/seKK5nO/xAKHHCCar876KpzRlleYN43QVl533CMWHRqgzFKfbhEzqfPLIhQHyOwKizOlCCmgm4eKqEMb8lMEN9DkJjwiTTjrEAQ09+XmKuH9NysMBFzKMTwpTfwai9vp0fnH7efrU794Oi8ZuBdsYUrjTpq+Fm4zggdCqTVea0KcBzEbGle6PVfvdZieSJCDRff8+DO3GAYRiwUo0+ilF6pi5kVzaX6mPk8OTKNMumTgkHVMVCVPk8uL1CctwgYo92Pj8j2uJn7i0O2DwsNEl4GwPYpGVELPD4Cvh98o+xVkEglO3Bj9KBCSCZlU8N9cUVLdzj1A+ItP2GPH3uijp1K5oEssh132PCQ7fuJQBGiHDhmhoco32tAhEpuHVdI5ZTcvE55g1cF1wl/DW7O2mpTdcUFSaS3jut9RxUKBUtwQ1pDHgoF8ZMQuG6n8DmQZCbIIi5wZe+mgqQg2WE0LufD/tw9+WOHzvnluG3132uq5Y6CWXdApQbRFSi+Iw2IjWqpkyA2QDkh0ScoCTaqZQ7ClUtAPQDRHSgJOKoV4sLgADnH4GroUmGjWoEqjI2eEhvm6eC5sEned7XBAVqgEe0JWcBRrS0oCA5w3h3RspAFHNX6MKWuDySmf3Cvu3ewU782v4JV2b3UtdOMiwxhgqtmKBLDg+sEh98EOYoMDTIV6OMZl93D1FHNViLGNenUkePwIANtdUnp64WNZ9xXFaaOapYcMQJLp44crTENtOCD0o4LHc+6Qg+mjmqGJjEqSqcOn05ImamDlvlSiuKx8boA6uiqmcHEUC6VOpIcLW6g7QsoBzBg4xlXlMMVKHgo9vw1LFMJ7LZKla1JJWjrtJWiQSmG1bjVFJq7x9OZ1elgqwLVb/BbgVLlxJNJIEmRpVmqnPi8kBRRcmmWKieeEUK8MithTUaXT7Cb0AqwyJEimgFrK3DGK41SZqKumCCJdE907HVceCVWKoJLEdlSeKly8fKDVxY2KZdgbQGuFBcfRB6Ilx6kLIJ1VBQXHjlR4Sw7enfBeWd4f27cXE/7tjFyhn8bGWVHakEBiJn0ssPhJDvABYBkx8FJ60yxtgAAcusIbecGf+EB/jYkPCpYSLBwlh79+eis/fHTvfUfn3qnP38G9ftPAKVwMlvcjGQtUpZOQoZeSOb+Ri2FvxFslsLC20Y8IKAszVLyQwY3s8kPD9xiTgKtH12B1U7O2h0ME7RyB2cgLWtSwpBU7uAMkHDesWGEKndwdoSEuoMTOV6oYEdTP3m1QyEVxinZDYUMuSRiXOVmKHkBKERoq9wMhREgYmW0BLkYqIwGzQ8WbjNSuRLnrgYyMbK4zAtSSRLnHgb7CUAReRY5+iPxU9t4ReGIpb/K9kIi4y6JXAB6HKvVCykvCkVE2bLJBi5RNkw2CI2yAW3SeEVzxLFyl+CNKUY0gL8NdEmrQChYMuxRFeKSA//G8ajl94zj37BXeCD1GNQqEJK4WC8C2R68x4FkXl0P/vgeVQEKhA6o39ke4GcPXfQx8P1wvX4mEi6Pp/7YXYz4Pw==</diagram></mxfile>
\ No newline at end of file
diff --git a/docs/research.md b/docs/research.md
index 73618d7..a3e86ff 100644
--- a/docs/research.md
+++ b/docs/research.md
@@ -33,6 +33,11 @@ this chip's features and limitations:
 - tiles can be flipped using OAM
 - no frame buffer
 
+Though this chip is documented very well from a programmer's perspective, we
+found very little documentation about any reverse-engineering of the chip's
+actual hardware. While our PPU provides mostly the same features as the NES's
+PPU, our design is entirely custom.
+
 ### Usage
 
 The NES PPU has a lot of capabilities, so here's a quick run-down of how the
@@ -93,210 +98,6 @@ int main() {
   setup();
   while(1) loop();
 }
-```
-
-## Custom PPU
-
-Here's a list of features our PPU should have:
-<!-- TODO: expand list with PPU spreadsheet -->
-
-- 320x240 @ 60Hz VGA output
-- single tilemap with room for 1024 tiles of 16x16 pixels
-- 8 colors per palette, with 4096 possible colors (12-bit color depth)
-- 512x448 background canvas with scrolling
-- NO background scrolling splits
-- 128 total sprites on screen (NO scanline sprite limit)
-- sprites are always drawn on top of the background layer
-- PPU control using DMA (dual-port asynchronous RAM)
-- tiles can be flipped using FAM or BAM
-- no frame buffer
-- vertical and horizontal sync output
-
-Notable differences:
-
-- NES nametable equivalent is called BAM (background attribute register)
-- NES OAM equivalent is called FAM (foreground attribute register)
-- 320x240 @ 60Hz output
-  
-  Since we're using VGA, we can't use custom resolutions without an
-  upscaler/downscaler. This resolution was chosen because it's exactly half of
-  the lowest standard VGA resolution 640x480.
-- No scanline sprite limit  
-  
-  Unless not imposing any sprite limit makes the hardware implementation
-  impossible, or much more difficult, this is a restriction that will likely
-  lead to frustrating debugging sessions, so will not be replicated in our
-  custom PPU.
-- Sprites are 16x16
-  
-  Most NES games already tile multiple 8x8 tiles together into "metatiles" to
-  create the illusion of larger sprites. This was likely done to save on memory
-  costs as RAM was expensive in the '80s, but since we're running on an FPGA
-  cost is irrelevant.
-- Single 1024 sprite tilemap shared between foreground and background sprites
-  
-  The NES OAM registers contain a bit to select which tilemap to use (of two),
-  which effectively expands each tile's index address by one byte. Instead of
-  creating the illusion of two separate memory areas for tiles, having one
-  large tilemap seems like a more sensible solution to indexed tiles.
-- 8 total palettes, with 8 colors each
-  
-  More colors is better. Increasing the total palette count is a very memory
-  intensive operation, while increaing the palette color count is likely slower
-  when looking up color values for each pixel on real hardware.
-- Sprites can be positioned paritally off-screen on all screen edges using only
-  the offset bits in the FAM register
-  
-  The NES has a separate PPUMASK register to control special color effects, and
-  to shift sprites off the left and top screen edges, as the sprite offsets
-  count from 0. Our PPU's FAM sprite offset bits count from -15, so the sprite
-  can shift past the top and left screen edges, as well as the standard bottom
-  and right edges.
-- No status line register, only V-sync and H-sync outputs are supplied back to
-  CPU
-  
-  The NES status line register contains some handy lines, such as a buggy
-  status line for reaching the max sprite count per scanline, and a status line
-  for detecting collisions between background and foreground sprites. Our PPU
-  doesn't have a scanline limit, and all hitbox detection is done in software.
-  Software hacks involving swapping tiles during a screen draw cycle can still
-  be achieved by counting the V-sync and H-sync pulses using interrupts.
-- No background scrolling splits
-  
-  This feature allows only part of the background canvas to be scrolled, while
-  another portion stays still. This was used to draw HUD elements on the
-  background layer for displaying things like health bars or score counters.
-  Since we are working with a higher foreground sprite limit, we'll use regular
-  foreground sprites to display HUD elements.
-- Sprites are always drawn on top of the background layer
-  
-  Our game doesn't need this capability for any visual effects. Leaving this
-  feature out will lead to a simpler hardware design
-
-### Hardware design schematics
-
-#### Top (level 1)
-
-![PPU top-level design](../assets/ppu-level-1.svg)
-
-Important notes:
-
-- The STM32 can reset the PPU. This line will also be connected to a physical
-  button on the FPGA.
-- The STM32 uses direct memory access to control the PPU.
-- The PPU's native resolution is 320x240. It works in this resolution as if it
-  is a valid VGA signal. The STM32 is also only aware of this resolution. This
-  resolution is referred to as "tiny" resolution. Because VGA-compatible LCD's
-  likely don't support this resolution due to low clock speed, a built-in
-  pixel-perfect 2X upscaler is chained after the PPU's "tiny" output. This
-  means that the display sees the resolution as 640x480, but the PPU and STM32
-  only work in 320x240.
-- The STM32 receives the TVSYNC and THSYNC lines from the PPU. These are the
-  VSYNC and HSYNC lines from the tiny VGA signal generator. These lines can be
-  used to trigger interrupts for counting frames, and to make sure no
-  read/write conflicts occur for protected memory regions in the PPU.
-- NVSYNC, NHSYNC and the RGB signals refer to the output of the native VGA
-  signal generator.
-
-#### Level 2
-
-![PPU level 2 design (data flows from top to bottom)](../assets/ppu-level-2.svg)
-
-Important notes:
-
-- The pixel fetch logic is pipelined in 5 stages:
-  1. - (Foreground sprite info) calculate if foreground sprite exists at
-     current pixel using FAM register
-     - (Background sprite info) get background sprite info from BAM register
-  2. - (Sprite render) calculate pixel to read from TMM based on sprite info
-  3. - (Compositor) get pixel with 'highest' priority (pick first foreground
-     sprite with non-transparent color at current pixel in order, fallback to
-     background)
-     - (Palette lookup) lookup palette color using palette register
-     - (VGA signal generator) output real color to VGA signal generator
-- The pipeline stages with two clock cycles contain an address set and memory
-  read step.
-- The pipeline takes 5 clock ticks in total. About 18 are available during each
-  pixel. For optimal display compatibility, the output color signal should be
-  stable before 50% of the pixel clock pulse width (9 clock ticks).
-- Since the "sprite info" and "sprite render" steps are fundamentally different
-  for the foreground and background layer, these components will be combined
-  into one for each layer respectively. They are separated in the above diagram
-  for pipeline stage illustration.
-- The BAX, FAM, and PAL registers are implemented in the component that
-  directly accesses them, but are exposed to the PPU RAM bus for writing.
-- Each foreground sprite render component holds its own sprite data copy from
-  the RAM in it's own cache memory. The cache updates are fetched during the
-  VBLANK time between each frame.
-
-#### Level 3
-
-This diagram has several flaws, but a significant amount of time has already
-been spent on these, so they are highlighted here instead of being fixed.
-
-![PPU level 3 design](../assets/ppu-level-3.svg)
-
-Flaws:
-
-- Pipeline stages 1-4 aren't properly connected in this diagram, see level 2
-  notes for proper functionality
-- The global RESET input resets all PPU RAM, but isn't connected to all RAM
-  ports
-- All DATA inputs on the same line as an ADDR output are connections to a
-  memory component. Not all of these are connected in the diagram, though they
-  should be.
-
-Important notes:
-
-- The background sprite and foreground sprite component internally share some
-  components for coordinate transformations
-- The foreground sprite component is only shown once here, but is cloned for
-  each foreground sprite the PPU allows.
-- The CIDX lines between the sprite and compositor components is shared by all
-  sprite components, and is such tri-state. A single sprite component outputs a
-  CIDX signal based on the \*EN signal from the compositor.
-- All DATA and ADDR lines are shared between all RAM ports. WEN inputs are
-  controlled by the address decoder.
-
-### Registers
-
-|Address|Size (bytes)|Alias|Description|
-|-|-|-|-|
-|`0x00000`|`0x00000`|TMM  |[tilemap memory][TMM]|
-|`0x00000`|`0x00000`|BAM  |[background attribute memory][BAM]|
-|`0x00000`|`0x00000`|FAM  |[foreground attribute memory][FAM]|
-|`0x00000`|`0x00000`|PAL  |[palettes][PAL]|
-|`0x00000`|`0x00000`|BAX  |[background auxiliary memory][BAX]|
-
-[TMM]: #tilemap-memory
-#### Tilemap memory
-
-- TODO: list format
-
-[BAM]: #background-attribute-memory
-#### Background attribute memory
-
-- TODO: list format
-
-[FAM]: #foreground-attribute-memory
-#### Foreground attribute memory
-
-- TODO: list format
-
-[PAL]: #palettes
-#### Palettes
-
-- TODO: list format
-
-[BAX]: #background-auxiliary-memory
-#### Background auxiliary memory
-
-- background scrolling
-
-[nesppuspecs]: https://www.copetti.org/writings/consoles/nes/
-[nesppudocs]: https://www.nesdev.org/wiki/PPU_programmer_reference
-[nesppupinout]: https://www.nesdev.org/wiki/PPU_pinout
-[custompputimings]: https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
 
 # Generating audio signals