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| author | NielsCoding <n.stunnebrink@student.avans.nl> | 2023-02-15 21:23:21 +0100 |
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| committer | NielsCoding <n.stunnebrink@student.avans.nl> | 2023-02-15 21:23:21 +0100 |
| commit | 0d601478e7809958a9f30d83a38428d401aa538a (patch) | |
| tree | 814f140a3ed4d954bea0fc6684a7879243a647fd /docs/architecture.md | |
| parent | c2071c621b4146ff7c6f918e86728237c9ff7c44 (diff) | |
architecture
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| -rw-r--r-- | docs/architecture.md | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/architecture.md b/docs/architecture.md index 4ebc674..635d8f8 100644 --- a/docs/architecture.md +++ b/docs/architecture.md @@ -277,4 +277,9 @@ These signals will be generated using PWM, this allows a digital signal to act a  This figure shows an example signal (in blue), created by the FPGA. and the corresponding analog signal (in red). +# level design +To create sprites the program to be used is aseprite, aseprite exports their sprite palette and puts them in our 2d map editor. For creating 2d levels were using Tiled as our 2d map editor. With this software, we can create and export our maps with our preferred technique. indexes are the technique we’re using to export our levels from the microcontroller to the FPGA. Below you see a picture explaining what indexes are and how they are implemented. + + +What kind of data type a specific index is and how large a number can go up to hasn't been decided yet. But I think it is going to be hexadecimal with around the size of 8 to 12 bits( two / three hexadecimal). |