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| author | lonkaars <loek@pipeframe.xyz> | 2023-02-14 16:16:52 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2023-02-14 16:16:52 +0100 |
| commit | 138cf645be7433022beead33025f8714e35c054f (patch) | |
| tree | 0616f1ee08345ad0fe18fa8cb89767d656648664 /docs/architecture.md | |
| parent | 480062b87c08a89976428befaac781432cd37474 (diff) | |
architecture top-level added
Diffstat (limited to 'docs/architecture.md')
| -rw-r--r-- | docs/architecture.md | 42 |
1 files changed, 29 insertions, 13 deletions
diff --git a/docs/architecture.md b/docs/architecture.md index eb20cce..ea07cdc 100644 --- a/docs/architecture.md +++ b/docs/architecture.md @@ -1,8 +1,18 @@ # General system architecture -<!-- TODO: top-level system architecture + context diagram --> + -## PPU +Important notes: + +- Gamepad 2 is optionally connected +- The PPU and APU are implemented on the FPGA +- The game logic and PPU/APU control logic runs on the STM32 only + +# Game controllers + +# STM32 software + +# PPU Here's a list of features our PPU has: @@ -79,9 +89,9 @@ Notable differences: Our game doesn't need this capability for any visual effects. Leaving this feature out will lead to a simpler hardware design -### Hardware design schematics +## Hardware design schematics -#### Top (level 1) +### Top (level 1)  @@ -104,7 +114,7 @@ Important notes: - NVSYNC, NHSYNC and the RGB signals refer to the output of the native VGA signal generator. -#### Level 2 +### Level 2  @@ -135,7 +145,7 @@ Important notes: the RAM in it's own cache memory. The cache updates are fetched during the VBLANK time between each frame. -#### Level 3 +### Level 3 This diagram has several flaws, but a significant amount of time has already been spent on these, so they are highlighted here instead of being fixed. @@ -162,11 +172,13 @@ Important notes: each foreground sprite the PPU allows. - The CIDX lines between the sprite and compositor components is shared by all sprite components, and is such tri-state. A single sprite component outputs a - CIDX signal based on the \*EN signal from the compositor. + CIDX signal based on the EN signal from the compositor. - All DATA and ADDR lines are shared between all RAM ports. WEN inputs are controlled by the address decoder. -### Registers +<!-- + +## Registers |Address|Size (bytes)|Alias|Description| |-|-|-|-| @@ -177,32 +189,36 @@ Important notes: |`0x00000`|`0x00000`|BAX |[background auxiliary memory][BAX]| [TMM]: #tilemap-memory -#### Tilemap memory +### Tilemap memory - TODO: list format [BAM]: #background-attribute-memory -#### Background attribute memory +### Background attribute memory - TODO: list format [FAM]: #foreground-attribute-memory -#### Foreground attribute memory +### Foreground attribute memory - TODO: list format [PAL]: #palettes -#### Palettes +### Palettes - TODO: list format [BAX]: #background-auxiliary-memory -#### Background auxiliary memory +### Background auxiliary memory - background scrolling +--> + [nesppuspecs]: https://www.copetti.org/writings/consoles/nes/ [nesppudocs]: https://www.nesdev.org/wiki/PPU_programmer_reference [nesppupinout]: https://www.nesdev.org/wiki/PPU_pinout [custompputimings]: https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc +# APU + |