apu note 2 freq

3 files changed, 116 insertions, 0 deletions

diff --git a/basys3/basys3.srcs/apu.vhd b/basys3/basys3.srcs/apu.vhd
new file mode 100644
index 0000000..ea2a342
--- /dev/null
+++ b/basys3/basys3.srcs/apu.vhd
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+
+entity apu is
+	port(
+		CLK100: in std_logic; -- system clock
+		RESET: in std_logic; -- global (async) system reset
+		DATA: in std_logic_vector(15 downto 0);
+        SOUND: out std_logic);
+
+		-- EN: in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers)
+		-- WEN: in std_logic; -- PPU VRAM write enable
+		-- ADDR: in std_logic_vector(15 downto 0); -- PPU VRAM ADDR
+		-- R,G,B: out std_logic_vector(3 downto 0);
+		-- NVSYNC, NHSYNC: out std_logic; -- native VGA out
+		-- TVSYNC, TVBLANK, THSYNC, THBLANK: out std_logic); -- tiny VGA out
+end apu;
+
+architecture Behavioral of apu is
+
+	component apu_note_to_frequency port (
+			data : in std_logic_vector(7 downto 0);
+			freq : out std_logic_vector(7 downto 0) --frequency
+		);
+	end component;
+	component apu_LUT_reader port (
+			clk   : in std_logic;
+			rst : in std_logic;
+			wave : in std_logic_vector(1 downto 0);
+			level : out std_logic_vector(7 downto 0)
+		);
+	end component;
+
+begin
+end architecture;
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diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
new file mode 100644
index 0000000..878da30
--- /dev/null
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity apu_note_to_frequency is
+    port (
+        -- clk : in std_logic;
+        -- rst : in std_logic;
+        data : in std_logic_vector(7 downto 0);
+        freq : out std_logic_vector(11 downto 0) --frequency
+    );
+end entity;
+
+architecture Behavioral of apu_note_to_frequency is
+signal buffSmall : std_logic_vector(7 downto 0) := (others => '0');
+signal buff : std_logic_vector(15 downto 0) := (others => '0');
+signal shift : integer;
+begin
+
+    shift <= to_integer(unsigned( data(2 downto 0) ));
+
+    buffSmall <= 
+        x"F0" when data(7 downto 3) = (x"C" & '0') else -- C  496
+        x"D0" when data(7 downto 3) = (x"C" & '1') else -- C# 464
+        x"B0" when data(7 downto 3) = (x"D" & '0') else -- D  432
+        x"A0" when data(7 downto 3) = (x"D" & '1') else -- D# 416
+        x"80" when data(7 downto 3) = (x"E" & '0') else -- E  384
+        x"70" when data(7 downto 3) = (x"F" & '0') else -- F  368
+        x"58" when data(7 downto 3) = (x"F" & '1') else -- F# 344
+        x"40" when data(7 downto 3) = (x"8" & '0') else -- G  320
+        x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304
+        x"20" when data(7 downto 3) = (x"A" & '0') else -- A  288
+        x"10" when data(7 downto 3) = (x"A" & '1') else -- A# 272
+        x"00" when data(7 downto 3) = (x"B" & '0') else -- B  256
+        x"01";
+
+    buff <= x"1" & buffSmall;
+    freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2)
+
+end architecture;
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diff --git a/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd b/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd
new file mode 100644
index 0000000..385071e
--- /dev/null
+++ b/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity apu_tb_note_to_frequency is
+end entity;
+
+architecture Behavioral of apu_tb_note_to_frequency is
+
+    component apu_note_to_frequency is
+        port (
+            data : in std_logic_vector(7 downto 0);
+            freq : out std_logic_vector(11 downto 0) --frequency
+        );
+    end component;
+
+    signal data : std_logic_vector(7 downto 0) := (others => '0');
+    signal freq : std_logic_vector(11 downto 0) := (others => '0');
+
+    signal OK : boolean := false;
+
+begin
+    UUT: apu_note_to_frequency
+    port map (
+        data => data,
+        freq => freq
+    );
+    
+    TB: process
+    begin
+        for I in 0 to 255 loop
+            data <= std_logic_vector(to_unsigned(I, 8));
+            wait for 4 ps;
+        end loop;
+    end process;
+
+end architecture;
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