spi not working on hardware

6 files changed, 444 insertions, 221 deletions

diff --git a/basys3/basys3.srcs/.gitignore b/basys3/basys3.srcs/.gitignore
index dd85c9b..e541866 100644
--- a/basys3/basys3.srcs/.gitignore
+++ b/basys3/basys3.srcs/.gitignore
@@ -1 +1,2 @@
 ppu_tb.vhd
+spi_tb.vhd
diff --git a/basys3/basys3.srcs/makefile b/basys3/basys3.srcs/makefile
index 61fab40..d37593c 100644
--- a/basys3/basys3.srcs/makefile
+++ b/basys3/basys3.srcs/makefile
@@ -1,4 +1,7 @@
-ppu_tb.vhd: ppu_tb.vhd.m4 ../../test/ppu-stm-integration-demo/test-image.tb.vhd
+all: ppu_tb.vhd spi_tb.vhd
+
+ppu_tb.vhd: ppu_tb.vhd.m4 ../../test/ppu-stm-integration-demo/test-image-ppu.tb.vhd
+spi_tb.vhd: spi_tb.vhd.m4 ../../test/ppu-stm-integration-demo/test-image-spi.tb.vhd
 
 %.vhd: %.vhd.m4
 	m4 -I../../test/ppu-stm-integration-demo/ $< > $@
diff --git a/basys3/basys3.srcs/ppu_tb.vhd.m4 b/basys3/basys3.srcs/ppu_tb.vhd.m4
index 0797c9f..97f0aef 100644
--- a/basys3/basys3.srcs/ppu_tb.vhd.m4
+++ b/basys3/basys3.srcs/ppu_tb.vhd.m4
@@ -1,3 +1,4 @@
+-- vim: ft=vhdl
 library ieee;
 library unisim;
 use ieee.std_logic_1164.all;
@@ -48,7 +49,7 @@ begin
 	
 	process
 	begin
-		-- undivert(`test-image.tb.vhd') -- m4 macro expansion (see makefile)
+		-- undivert(`test-image-ppu.tb.vhd') -- m4 macro expansion (see makefile)
 		wait; -- stop after one loop (process loops in simulator)
 	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd
index 8e4b8aa..255f38b 100644
--- a/basys3/basys3.srcs/spi_tb.vhd
+++ b/basys3/basys3.srcs/spi_tb.vhd
@@ -1,3 +1,4 @@
+-- vim: ft=vhdl
 library ieee;
 library unisim;
 
@@ -25,7 +26,7 @@ begin
 
 	process
 	begin
-		for i in 0 to 10000 loop
+		while true loop
 			wait for 5 ns;
 			SYSCLK <= '1';
 			wait for 5 ns;
@@ -36,227 +37,397 @@ begin
 
 	process
 	begin
-		for i in 0 to 2 loop
-			-- data = 0b01010110010100001001110011111111 (0x56509cff)
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '0';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-
-			SPI_DATA <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '1';
-			wait for 50 ns;
-			SPI_CLK <= '0';
-		end loop;
+		-- -- 0xdc00: 0f0f
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+--
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '0';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+-- 0xffff: ffff
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+--
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+SPI_DATA <= '1';
+wait for 50 ns;
+SPI_CLK <= '1';
+wait for 50 ns;
+SPI_CLK <= '0';
+
+ -- m4 macro expansion (see makefile)
 
-		wait for 50 ns;
-		SPI_CLK <= '1';
-		wait for 50 ns;
-		SPI_CLK <= '0';
-		wait for 50 ns;
-		SPI_CLK <= '1';
-		wait for 50 ns;
-		SPI_CLK <= '0';
-		wait for 50 ns;
-		SPI_CLK <= '1';
-		wait for 50 ns;
-		SPI_CLK <= '0';
-		wait for 50 ns;
-		SPI_CLK <= '1';
-		wait for 50 ns;
-		SPI_CLK <= '0';
-		wait for 50 ns;
-		SPI_CLK <= '1';
-		wait for 50 ns;
-		SPI_CLK <= '0';
-		wait for 50 ns;
 		RESET <= '1';
 		wait for 50 ns;
 		RESET <= '0';
-
-
 		wait; -- stop for simulator
 	end process;
 end;
diff --git a/basys3/basys3.srcs/spi_tb.vhd.m4 b/basys3/basys3.srcs/spi_tb.vhd.m4
new file mode 100644
index 0000000..cf76b2c
--- /dev/null
+++ b/basys3/basys3.srcs/spi_tb.vhd.m4
@@ -0,0 +1,47 @@
+-- vim: ft=vhdl
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+use work.ppu_consts.all;
+
+entity spi_tb is
+end spi_tb;
+
+architecture behavioral of spi_tb is
+	signal SYSCLK : std_logic := '0';
+	signal SPI_CLK : std_logic := '0';
+	signal SPI_DATA : std_logic := '0';
+	signal RESET : std_logic := '0';
+begin
+	uut : entity work.spi port map(
+		SYSCLK => SYSCLK,
+		RESET => RESET,
+		DO => open,
+		DI => SPI_DATA,
+		DCK => SPI_CLK,
+		WEN => open);
+
+	process
+	begin
+		while true loop
+			wait for 5 ns;
+			SYSCLK <= '1';
+			wait for 5 ns;
+			SYSCLK <= '0';
+		end loop;
+		wait; -- stop for simulator
+	end process;
+
+	process
+	begin
+		-- undivert(`test-background-color-spi.tb.vhd') -- m4 macro expansion (see makefile)
+
+		RESET <= '1';
+		wait for 50 ns;
+		RESET <= '0';
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 19bbeec..f90ecdb 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="108"/>
+    <Option Name="WTXSimLaunchSim" Val="118"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>