WIP addr_dec timing check + ppu address bus fix

6 files changed, 242 insertions, 249 deletions

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 9cf1bc0..2425edc 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -8,7 +8,6 @@ use work.ppu_consts.all;
 entity ppu is port(
 	CLK100 : in std_logic; -- system clock
 	RESET : in std_logic; -- global (async) system reset
-	EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers)
 	WEN : in std_logic; -- PPU VRAM write enable
 	ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR
 	DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
@@ -26,43 +25,43 @@ architecture Behavioral of ppu is
 		COMP_PAL : out std_logic; -- compositor + palette lookup
 		DONE : out std_logic); -- last pipeline stage done
 	end component;
-	component ppu_addr_dec port( -- pipeline clock edge generator
+	component ppu_addr_dec port( -- address decoder
 		WEN : in std_logic; -- EXT write enable
 		TMM_WEN,
 		BAM_WEN,
 		FAM_WEN,
 		PAL_WEN,
 		AUX_WEN : out std_logic; -- write enable MUX
-		EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI)
 		ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in
-		TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-		BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-		FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-		PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-		AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
-		TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-		BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-		FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-		PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-		AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
+		TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+		BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+		FAM_ADDR : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
+		PAL_ADDR : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
+		AUX_ADDR : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
 	end component;
 	component ppu_bam port( -- BAM block memory
 		clka : in std_logic;
-		rsta : in std_logic;
-		wea : in std_logic_vector(0 downto 0);
+		wea : in std_logic_vector(0 to 0);
 		addra : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
 		dina : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
-		douta : out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
-		rsta_busy : out std_logic);
+		clkb : in std_logic;
+		rstb : in std_logic;
+		addrb : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+		doutb : out std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+		rsta_busy : out std_logic;
+		rstb_busy : out std_logic);
 	end component;
 	component ppu_tmm port( -- TMM block memory
 		clka : in std_logic;
-		rsta : in std_logic;
-		wea : in std_logic_vector(0 downto 0);
+		wea : in std_logic_vector(0 to 0);
 		addra : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
 		dina : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
-		douta : out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
-		rsta_busy : out std_logic);
+		clkb : in std_logic;
+		rstb : in std_logic;
+		addrb : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+		doutb : out std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+		rsta_busy : out std_logic;
+		rstb_busy : out std_logic);
 	end component;
 	component ppu_aux port(
 		CLK : in std_logic; -- system clock
@@ -169,16 +168,13 @@ architecture Behavioral of ppu is
 	signal SYSCLK, SYSRST : std_logic; -- system clock and reset
 	signal PL_SPRITE, PL_COMP_PAL, PL_DONE : std_logic; -- pipeline stages
 	signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic;
-	signal TMM_AI, TMM_AO : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-	signal BAM_AI, BAM_AO : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-	signal FAM_AI, FAM_AO : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-	signal PAL_AI, PAL_AO : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-	signal AUX_AI, AUX_AO : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
-	signal TMM_DO : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
-	signal BAM_DO : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
-	signal FAM_DO : std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0);
-	signal PAL_DO : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0);
-	signal AUX_DO : std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0);
+	signal TMM_W_ADDR, TMM_R_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0); -- read/write TMM addr (dual port)
+	signal BAM_W_ADDR, BAM_R_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0); -- read/write BAM addr (dual port)
+	signal TMM_R_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0); -- internal read TMM data
+	signal BAM_R_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0); -- internal read BAM data
+	signal FAM_W_ADDR : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- write only FAM addr
+	signal PAL_W_ADDR : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- write only PAL addr
+	signal AUX_W_ADDR : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- write only AUX addr
 	signal CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0);
 	signal BG_EN : std_logic;
 	signal FG_EN, FG_HIT : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
@@ -195,15 +191,6 @@ begin
 	SYSCLK <= CLK100;
 	SYSRST <= RESET;
 
-	-- internal unused lines
-	--
-	-- these lines would be used if components use memory blocks as RAM blocks
-	-- (like how TMM and BAM work), the registers of these memory regions are
-	-- directly exposed internally, and are as such not used as RAM blocks
-	AUX_AI <= (others => '0');
-	FAM_AI <= (others => '0');
-	PAL_AI <= (others => '0');
-
 	TVBLANK <= TINY_VBLANK;
 	TVSYNC <= TINY_VSYNC;
 	THBLANK <= TINY_HBLANK;
@@ -219,19 +206,13 @@ begin
 		DONE => PL_DONE);
 
 	address_decoder : component ppu_addr_dec port map(
-		EN => EN,
 		WEN => WEN,
 		ADDR => ADDR,
-		TMM_AI => TMM_AI,
-		BAM_AI => BAM_AI,
-		FAM_AI => FAM_AI,
-		PAL_AI => PAL_AI,
-		AUX_AI => AUX_AI,
-		TMM_AO => TMM_AO,
-		BAM_AO => BAM_AO,
-		FAM_AO => FAM_AO,
-		PAL_AO => PAL_AO,
-		AUX_AO => AUX_AO,
+		TMM_ADDR => TMM_W_ADDR,
+		BAM_ADDR => BAM_W_ADDR,
+		FAM_ADDR => FAM_W_ADDR,
+		PAL_ADDR => PAL_W_ADDR,
+		AUX_ADDR => AUX_W_ADDR,
 		TMM_WEN => TMM_WEN,
 		BAM_WEN => BAM_WEN,
 		FAM_WEN => FAM_WEN,
@@ -240,26 +221,32 @@ begin
 
 	background_attribute_memory : component ppu_bam port map(
 		clka => SYSCLK,
-		rsta => SYSRST,
 		wea => (others => BAM_WEN),
-		addra => BAM_AO,
+		addra => BAM_W_ADDR,
 		dina => DATA(PPU_BAM_DATA_WIDTH-1 downto 0),
-		douta => BAM_DO,
-		rsta_busy => open);
+		clkb => SYSCLK,
+		rstb => SYSRST,
+		addrb => BAM_R_ADDR,
+		doutb => BAM_R_DATA,
+		rsta_busy => open,
+		rstb_busy => open);
 	tilemap_memory : component ppu_tmm port map(
 		clka => SYSCLK,
-		rsta => SYSRST,
 		wea => (others => TMM_WEN),
-		addra => TMM_AO,
+		addra => TMM_W_ADDR,
 		dina => DATA(PPU_TMM_DATA_WIDTH-1 downto 0),
-		douta => TMM_DO,
-		rsta_busy => open);
+		clkb => SYSCLK,
+		rstb => SYSRST,
+		addrb => TMM_R_ADDR,
+		doutb => TMM_R_DATA,
+		rsta_busy => open,
+		rstb_busy => open);
 
 	aux : component ppu_aux port map(
 		CLK => SYSCLK,
 		RESET => SYSRST,
 		AUX_WEN => AUX_WEN,
-		AUX_ADDR => AUX_AO,
+		AUX_ADDR => AUX_W_ADDR,
 		AUX_DATA => DATA(PPU_AUX_DATA_WIDTH-1 downto 0),
 		BG_SHIFT_X => BG_SHIFT_X,
 		BG_SHIFT_Y => BG_SHIFT_Y,
@@ -273,10 +260,10 @@ begin
 		Y => Y,
 		BG_SHIFT_X => BG_SHIFT_X,
 		BG_SHIFT_Y => BG_SHIFT_Y,
-		BAM_ADDR => BAM_AI,
-		BAM_DATA => BAM_DO,
-		TMM_ADDR => TMM_AI,
-		TMM_DATA => TMM_DO,
+		BAM_ADDR => BAM_R_ADDR,
+		BAM_DATA => BAM_R_DATA,
+		TMM_ADDR => TMM_R_ADDR,
+		TMM_DATA => TMM_R_DATA,
 		CIDX => CIDX);
 
 	foreground_sprites : for FG_IDX in 0 to PPU_FG_SPRITE_COUNT-1 generate
@@ -291,10 +278,10 @@ begin
 				FETCH => FG_FETCH,
 				VBLANK => TINY_VBLANK,
 				FAM_WEN => FAM_WEN,
-				FAM_ADDR => FAM_AO,
+				FAM_ADDR => FAM_W_ADDR,
 				FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
-				TMM_ADDR => TMM_AI,
-				TMM_DATA => TMM_DO,
+				TMM_ADDR => TMM_R_ADDR,
+				TMM_DATA => TMM_R_DATA,
 				CIDX => CIDX,
 				HIT => FG_HIT(FG_IDX));
 	end generate;
@@ -309,7 +296,7 @@ begin
 		CIDX => CIDX,
 		RESET => SYSRST,
 		PAL_WEN => PAL_WEN,
-		PAL_ADDR => PAL_AO,
+		PAL_ADDR => PAL_W_ADDR,
 		PAL_DATA => DATA(PPU_PAL_DATA_WIDTH-1 downto 0),
 		R => UR,
 		G => UG,
diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhd b/basys3/basys3.srcs/ppu_addr_dec.vhd
index e0c374f..33f247c 100644
--- a/basys3/basys3.srcs/ppu_addr_dec.vhd
+++ b/basys3/basys3.srcs/ppu_addr_dec.vhd
@@ -4,8 +4,7 @@ use ieee.std_logic_1164.all;
 --use ieee.numeric_std.all;
 use work.ppu_consts.all;
 
-entity ppu_addr_dec is port(
-	EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI)
+entity ppu_addr_dec is port( -- address decoder
 	WEN : in std_logic; -- EXT write enable
 	TMM_WEN,
 	BAM_WEN,
@@ -13,27 +12,22 @@ entity ppu_addr_dec is port(
 	PAL_WEN,
 	AUX_WEN : out std_logic; -- write enable MUX
 	ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in
-	TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-	BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-	FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-	PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-	AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
-	TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-	BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-	FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-	PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-	AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
+	TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	FAM_ADDR : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
+	PAL_ADDR : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
+	AUX_ADDR : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
 end ppu_addr_dec;
 
 architecture Behavioral of ppu_addr_dec is
 	signal TMM_RANGE, BAM_RANGE, FAM_RANGE, PAL_RANGE, AUX_RANGE : std_logic := '0'; -- ADDR in range of memory area
 begin
 	-- address MUX
-	TMM_AO <= ADDR(PPU_TMM_ADDR_WIDTH-1 downto 0) when EN = '1' else TMM_AI;
-	BAM_AO <= ADDR(PPU_BAM_ADDR_WIDTH-1 downto 0) when EN = '1' else BAM_AI;
-	FAM_AO <= ADDR(PPU_FAM_ADDR_WIDTH-1 downto 0) when EN = '1' else FAM_AI;
-	PAL_AO <= ADDR(PPU_PAL_ADDR_WIDTH-1 downto 0) when EN = '1' else PAL_AI;
-	AUX_AO <= ADDR(PPU_AUX_ADDR_WIDTH-1 downto 0) when EN = '1' else AUX_AI;
+	TMM_ADDR <= ADDR(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	BAM_ADDR <= ADDR(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	FAM_ADDR <= ADDR(PPU_FAM_ADDR_WIDTH-1 downto 0);
+	PAL_ADDR <= ADDR(PPU_PAL_ADDR_WIDTH-1 downto 0);
+	AUX_ADDR <= ADDR(PPU_AUX_ADDR_WIDTH-1 downto 0);
 
 	-- WEN MUX
 	TMM_WEN <= TMM_RANGE and WEN;
diff --git a/basys3/basys3.srcs/ppu_addr_dec_tb.vhd b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd
index f31ee67..051f305 100644
--- a/basys3/basys3.srcs/ppu_addr_dec_tb.vhd
+++ b/basys3/basys3.srcs/ppu_addr_dec_tb.vhd
@@ -12,7 +12,6 @@ end ppu_addr_dec_tb;
 
 architecture behavioral of ppu_addr_dec_tb is
 	component ppu_addr_dec port(
-		EN : in std_logic; -- EXT *ADDR enable (switch *AO to ADDR instead of *AI)
 		WEN : in std_logic; -- EXT write enable
 		TMM_WEN,
 		BAM_WEN,
@@ -20,34 +19,22 @@ architecture behavioral of ppu_addr_dec_tb is
 		PAL_WEN,
 		AUX_WEN : out std_logic; -- write enable MUX
 		ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- address in
-		TMM_AI : in std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-		BAM_AI : in std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-		FAM_AI : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-		PAL_AI : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-		AUX_AI : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
-		TMM_AO : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-		BAM_AO : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-		FAM_AO : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-		PAL_AO : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-		AUX_AO : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
+		TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+		BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+		FAM_ADDR : out std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
+		PAL_ADDR : out std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
+		AUX_ADDR : out std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0));
 	end component;
-	signal EN : std_logic;
 	signal WEN : std_logic;
 	signal TMM_WEN, BAM_WEN, FAM_WEN, PAL_WEN, AUX_WEN : std_logic;
 	signal ADDR : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0);
-	signal TMM_AI : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-	signal BAM_AI : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-	signal FAM_AI : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-	signal PAL_AI : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-	signal AUX_AI : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
-	signal TMM_AO : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-	signal BAM_AO : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
-	signal FAM_AO : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
-	signal PAL_AO : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
-	signal AUX_AO : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
+	signal TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	signal BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	signal FAM_ADDR : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0);
+	signal PAL_ADDR : std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0);
+	signal AUX_ADDR : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0);
 begin
 	uut : ppu_addr_dec port map(
-    EN => EN,
     WEN => WEN,
     TMM_WEN => TMM_WEN,
     BAM_WEN => BAM_WEN,
@@ -55,26 +42,14 @@ begin
     PAL_WEN => PAL_WEN,
     AUX_WEN => AUX_WEN,
     ADDR => ADDR,
-    TMM_AI => TMM_AI,
-    BAM_AI => BAM_AI,
-    FAM_AI => FAM_AI,
-    PAL_AI => PAL_AI,
-    AUX_AI => AUX_AI,
-    TMM_AO => TMM_AO,
-    BAM_AO => BAM_AO,
-    FAM_AO => FAM_AO,
-    PAL_AO => PAL_AO,
-    AUX_AO => AUX_AO);
+    TMM_ADDR => TMM_ADDR,
+    BAM_ADDR => BAM_ADDR,
+    FAM_ADDR => FAM_ADDR,
+    PAL_ADDR => PAL_ADDR,
+    AUX_ADDR => AUX_ADDR);
 
-  EN <= '1';
   WEN <= '1';
 
-  TMM_AI <= (others => '1');
-  BAM_AI <= (others => '0');
-  FAM_AI <= (others => '1');
-  PAL_AI <= (others => '0');
-  AUX_AI <= (others => '0');
-
 	tb : process
 	begin
 		for i in 0 to 65535 loop
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
index e299ea1..9f293d6 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
@@ -13,12 +13,12 @@
         "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
         "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
         "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -27,49 +27,49 @@
         "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
         "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Write_Depth_A": [ { "value": "1200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Read_Width_A": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
-        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
         "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "Write_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Read_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "READ_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
-        "Use_RSTA_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
-        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
-        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
         "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
         "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -92,16 +92,16 @@
         "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
         "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
         "C_INIT_FILE": [ { "value": "ppu_bam.mem", "resolve_type": "generated", "usage": "all" } ],
-        "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
         "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
@@ -109,13 +109,13 @@
         "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "NO_CHANGE", "resolve_type": "generated", "usage": "all" } ],
         "C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_DEPTH_A": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRA_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
         "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
@@ -123,14 +123,14 @@
         "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
         "C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_DEPTH_B": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_DEPTH_B": [ { "value": "1200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -143,7 +143,7 @@
         "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
-        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -155,7 +155,7 @@
         "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
         "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     2.6537 mW", "resolve_type": "generated", "usage": "all" } ]
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     4.9121 mW", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "artix7" } ],
@@ -186,12 +186,15 @@
     "boundary": {
       "ports": {
         "clka": [ { "direction": "in", "driver_value": "0" } ],
-        "rsta": [ { "direction": "in", "driver_value": "0" } ],
         "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
         "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
-        "douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
-        "rsta_busy": [ { "direction": "out" } ]
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "rstb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
+        "rsta_busy": [ { "direction": "out" } ],
+        "rstb_busy": [ { "direction": "out" } ]
       },
       "interfaces": {
         "CLK.ACLK": {
@@ -234,10 +237,27 @@
             "ADDR": [ { "physical_name": "addra" } ],
             "CLK": [ { "physical_name": "clka" } ],
             "DIN": [ { "physical_name": "dina" } ],
-            "DOUT": [ { "physical_name": "douta" } ],
-            "RST": [ { "physical_name": "rsta" } ],
             "WE": [ { "physical_name": "wea" } ]
           }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "RST": [ { "physical_name": "rstb" } ]
+          }
         }
       },
       "memory_maps": {
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
index 9663635..958b9b9 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
@@ -13,12 +13,12 @@
         "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
         "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
         "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -31,45 +31,45 @@
         "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
         "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Write_Depth_A": [ { "value": "53248", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Read_Width_A": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
-        "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
         "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "Write_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Read_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "READ_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Fill_Remaining_Memory_Locations": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
-        "Use_RSTA_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
-        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
-        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
         "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
         "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -92,16 +92,16 @@
         "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
         "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
         "C_INIT_FILE": [ { "value": "ppu_tmm.mem", "resolve_type": "generated", "usage": "all" } ],
-        "C_USE_DEFAULT_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
-        "C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
         "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
@@ -109,13 +109,13 @@
         "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "NO_CHANGE", "resolve_type": "generated", "usage": "all" } ],
         "C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
         "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
@@ -123,14 +123,14 @@
         "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
         "C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_DEPTH_B": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_READ_DEPTH_B": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -143,7 +143,7 @@
         "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
-        "C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -155,7 +155,7 @@
         "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_COUNT_36K_BRAM": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ],
         "C_COUNT_18K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
-        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     13.861152 mW", "resolve_type": "generated", "usage": "all" } ]
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     25.994176 mW", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "artix7" } ],
@@ -186,12 +186,15 @@
     "boundary": {
       "ports": {
         "clka": [ { "direction": "in", "driver_value": "0" } ],
-        "rsta": [ { "direction": "in", "driver_value": "0" } ],
         "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
-        "douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
-        "rsta_busy": [ { "direction": "out" } ]
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "rstb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
+        "rsta_busy": [ { "direction": "out" } ],
+        "rstb_busy": [ { "direction": "out" } ]
       },
       "interfaces": {
         "CLK.ACLK": {
@@ -234,10 +237,27 @@
             "ADDR": [ { "physical_name": "addra" } ],
             "CLK": [ { "physical_name": "clka" } ],
             "DIN": [ { "physical_name": "dina" } ],
-            "DOUT": [ { "physical_name": "douta" } ],
-            "RST": [ { "physical_name": "rsta" } ],
             "WE": [ { "physical_name": "wea" } ]
           }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "RST": [ { "physical_name": "rstb" } ]
+          }
         }
       },
       "memory_maps": {
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 4060a21..87ec9fe 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,20 +61,20 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="113"/>
+    <Option Name="WTXSimLaunchSim" Val="118"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="4"/>
-    <Option Name="WTModelSimExportSim" Val="4"/>
-    <Option Name="WTQuestaExportSim" Val="4"/>
+    <Option Name="WTXSimExportSim" Val="10"/>
+    <Option Name="WTModelSimExportSim" Val="10"/>
+    <Option Name="WTQuestaExportSim" Val="10"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="4"/>
-    <Option Name="WTRivieraExportSim" Val="4"/>
-    <Option Name="WTActivehdlExportSim" Val="4"/>
+    <Option Name="WTVcsExportSim" Val="10"/>
+    <Option Name="WTRivieraExportSim" Val="10"/>
+    <Option Name="WTActivehdlExportSim" Val="10"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -93,7 +93,7 @@
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/ppu_consts.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -268,35 +268,27 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
+        <Option Name="TopModule" Val="ppu_addr_dec_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="SimMode" Val="post-synthesis"/>
         <Option Name="PamDesignTestbench" Val=""/>
         <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
-        <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
-    <FileSet Name="ppu_bam" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_bam" RelGenDir="$PGENDIR/ppu_bam">
-      <File Path="$PSRCDIR/sources_1/ip/ppu_bam/ppu_bam.xci">
+    <FileSet Name="ppu_tmm" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_tmm" RelGenDir="$PGENDIR/ppu_tmm">
+      <File Path="$PSRCDIR/sources_1/ip/ppu_tmm/ppu_tmm.xci">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -304,12 +296,12 @@
         </FileInfo>
       </File>
       <Config>
-        <Option Name="TopModule" Val="ppu_bam"/>
+        <Option Name="TopModule" Val="ppu_tmm"/>
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
-    <FileSet Name="ppu_tmm" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_tmm" RelGenDir="$PGENDIR/ppu_tmm">
-      <File Path="$PSRCDIR/sources_1/ip/ppu_tmm/ppu_tmm.xci">
+    <FileSet Name="ppu_bam" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_bam" RelGenDir="$PGENDIR/ppu_bam">
+      <File Path="$PSRCDIR/sources_1/ip/ppu_bam/ppu_bam.xci">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -317,7 +309,8 @@
         </FileInfo>
       </File>
       <Config>
-        <Option Name="TopModule" Val="ppu_tmm"/>
+        <Option Name="TopModule" Val="ppu_bam"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
@@ -344,7 +337,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -354,7 +347,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ppu_bam_synth_1" Type="Ft3:Synth" SrcSet="ppu_bam" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_bam_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1">
+    <Run Id="ppu_tmm_synth_1" Type="Ft3:Synth" SrcSet="ppu_tmm" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_tmm_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -364,9 +357,11 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ppu_tmm_synth_1" Type="Ft3:Synth" SrcSet="ppu_tmm" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_tmm_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1">
+    <Run Id="ppu_bam_synth_1" Type="Ft3:Synth" SrcSet="ppu_bam" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_bam_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -391,7 +386,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ppu_bam_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_bam_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1">
+    <Run Id="ppu_tmm_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_tmm_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -408,9 +403,11 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ppu_tmm_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_tmm_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1">
+    <Run Id="ppu_bam_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_bam_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>