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authorlonkaars <loek@pipeframe.xyz>2023-03-08 13:32:41 +0100
committerlonkaars <loek@pipeframe.xyz>2023-03-08 13:32:41 +0100
commit77090b9a6a9052848ccf233a8f8bee59418da0d8 (patch)
treef4ec761366f0a08d8f075f2e954c7fb59b058feb /basys3/basys3.xpr
parentb9497d796a5d06ad937c0951226099702c3c69e9 (diff)
scaffold vga display controller and upscaler
Diffstat (limited to 'basys3/basys3.xpr')
-rw-r--r--basys3/basys3.xpr71
1 files changed, 55 insertions, 16 deletions
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 1250176..4134b4d 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -68,13 +68,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="10"/>
- <Option Name="WTModelSimExportSim" Val="10"/>
- <Option Name="WTQuestaExportSim" Val="10"/>
+ <Option Name="WTXSimExportSim" Val="11"/>
+ <Option Name="WTModelSimExportSim" Val="11"/>
+ <Option Name="WTQuestaExportSim" Val="11"/>
<Option Name="WTIesExportSim" Val="0"/>
- <Option Name="WTVcsExportSim" Val="10"/>
- <Option Name="WTRivieraExportSim" Val="10"/>
- <Option Name="WTActivehdlExportSim" Val="10"/>
+ <Option Name="WTVcsExportSim" Val="11"/>
+ <Option Name="WTRivieraExportSim" Val="11"/>
+ <Option Name="WTActivehdlExportSim" Val="11"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -166,12 +166,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_vga_tiny.vhd">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
<File Path="$PSRCDIR/ppu_comp.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -184,15 +178,15 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/ppu_vga_native.vhd">
+ <File Path="$PSRCDIR/apu_lut_reader.vhd">
<FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/apu_lut_reader.vhd">
- <FileInfo>
- <Attr Name="UserDisabled" Val="1"/>
+ <File Path="$PSRCDIR/ppu_dispctl.vhd">
+ <FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -321,6 +315,20 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
+ <FileSet Name="ppu_dispctl_slbuf" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ppu_dispctl_slbuf" RelGenDir="$PGENDIR/ppu_dispctl_slbuf">
+ <File Path="$PSRCDIR/sources_1/ip/ppu_dispctl_slbuf/ppu_dispctl_slbuf.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="ppu_dispctl_slbuf"/>
+ <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -374,6 +382,18 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
+ <Run Id="ppu_dispctl_slbuf_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_slbuf" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_slbuf_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
@@ -426,6 +446,25 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
+ <Run Id="ppu_dispctl_slbuf_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_slbuf_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
</Runs>
<Board>
<Jumpers/>