more debugging WIP

4 files changed, 45 insertions, 35 deletions

diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
index 4f017f3..1465a58 100644
--- a/basys3/basys3.srcs/ppu_dispctl.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -57,28 +57,6 @@ begin
 	ADDR_I <= std_logic_vector(resize(T_POS_X, ADDR_I'length)) when T_POS_Y(0) = '0' else std_logic_vector(resize(T_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH);
 
 	T_POS_Y <= U_POS_Y;
-	-- tiny VCOUNT and HCOUNT
-	process(TPIXCLK, RESET)
-		variable TMP_T_POS_X : unsigned(PPU_SCREEN_T_POS_X_WIDTH-1 downto 0) := (others => '0');
-		variable TMP_THBLANK, TMP_TVBLANK : std_logic := '0';
-	begin
-		if RESET = '1' then
-			TMP_THBLANK := '0'; -- TODO
-			TMP_TVBLANK := '0'; -- TODO
-		elsif rising_edge(TPIXCLK) then
-			T_POS_X <= TMP_T_POS_X;
-
-			THBLANK <= TMP_THBLANK;
-			TVBLANK <= TMP_TVBLANK;
-
-			if NACTIVE = '1' then
-				TMP_T_POS_X := TMP_T_POS_X + 1;
-				if TMP_T_POS_X >= PPU_SCREEN_WIDTH then
-					TMP_T_POS_X := (others => '0');
-				end if;
-			end if;
-		end if;
-	end process;
 
 	X <= std_logic_vector(T_POS_X) when NACTIVE = '1' else (others => '0');
 	Y <= std_logic_vector(T_POS_Y) when NACTIVE = '1' else (others => '0');
@@ -92,26 +70,33 @@ begin
 	GO <= DATA_O(7 downto 4) when NACTIVE = '1' else (others => '0');
 	BO <= DATA_O(3 downto 0) when NACTIVE = '1' else (others => '0');
 
-	-- native (+upscaled) VCOUNT and HCOUNT
-	process(NPIXCLK, RESET)
+	-- tiny VCOUNT and HCOUNT
+	process(TPIXCLK, NPIXCLK, RESET)
+		variable TMP_T_POS_X : unsigned(PPU_SCREEN_T_POS_X_WIDTH-1 downto 0) := (others => '0');
+		variable TMP_THBLANK, TMP_TVBLANK : std_logic := '0';
 		variable TMP_NHCOUNT, TMP_NVCOUNT : unsigned(PPU_VGA_SIGNAL_PIXEL_WIDTH-1 downto 0) := (others => '0');
 		variable TMP_NHACTIVE, TMP_NVACTIVE : std_logic := '0';
 		variable TMP_NHSYNC, TMP_NVSYNC : std_logic := '0';
+		variable TMP_NACTIVE : std_logic := '0';
 	begin
 		if RESET = '1' then
 			TMP_NHCOUNT := (others => '0');
 			TMP_NVCOUNT := (others => '0');
 			TMP_NHACTIVE := '0';
 			TMP_NVACTIVE := '0';
+			TMP_THBLANK := '0'; -- TODO
+			TMP_TVBLANK := '0'; -- TODO
 			TMP_NVSYNC := '0';
 			TMP_NHSYNC := '0';
-		elsif rising_edge(NPIXCLK) then
+		end if;
+		-- native (+upscaled) VCOUNT and HCOUNT
+		if rising_edge(NPIXCLK) then
 			-- sync write (needs to be here to happen on rising edge)
 			NVCOUNT <= TMP_NVCOUNT;
 			NHCOUNT <= TMP_NHCOUNT;
 			NHACTIVE <= TMP_NHACTIVE;
 			NVACTIVE <= TMP_NVACTIVE;
-			NACTIVE <= TMP_NHACTIVE and TMP_NVACTIVE;
+			NACTIVE <= TMP_NACTIVE;
 			NVSYNC <= TMP_NVSYNC;
 			NHSYNC <= TMP_NHSYNC;
 			N_POS_X <= resize(TMP_NHCOUNT - PPU_VGA_H_PORCH_BACK, N_POS_X'length) when TMP_NHACTIVE = '1' else (others => '0');
@@ -140,11 +125,26 @@ begin
 			-- horizontal display area (active)
 			if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK then TMP_NHACTIVE := '1'; end if;
 			if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE then TMP_NHACTIVE := '0'; end if;
+			TMP_NACTIVE := TMP_NHACTIVE and TMP_NVACTIVE;
 
 			-- horizontal sync period
 			if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE then TMP_NHSYNC := '1'; end if;
 			if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE + PPU_VGA_H_SYNC then TMP_NHSYNC := '0'; end if;
 		end if;
+
+		if falling_edge(TPIXCLK) then -- NOTE: falling edge used because of clock offset of 90 (should be 270)
+			T_POS_X <= TMP_T_POS_X;
+
+			THBLANK <= TMP_THBLANK;
+			TVBLANK <= TMP_TVBLANK;
+
+			if TMP_NACTIVE = '1' then
+				TMP_T_POS_X := TMP_T_POS_X + 1;
+				if TMP_T_POS_X >= PPU_SCREEN_WIDTH then
+					TMP_T_POS_X := (others => '0');
+				end if;
+			end if;
+		end if;
 	end process;
 	ACTIVE <= NACTIVE;
 
diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd
index 3de3d23..67b7e1c 100644
--- a/basys3/basys3.srcs/ppu_pceg.vhd
+++ b/basys3/basys3.srcs/ppu_pceg.vhd
@@ -13,6 +13,7 @@ entity ppu_pceg is port(
 end ppu_pceg;
 
 architecture Behavioral of ppu_pceg is
+	signal CLK_IDX_T : natural range 0 to PPU_PCEG_TOTAL_STAGES+1 := 0;
 begin
 	process(CLK, RESET)
 		variable CLK_IDX : natural range 0 to PPU_PCEG_TOTAL_STAGES+1 := 0;
@@ -24,7 +25,7 @@ begin
 			SPRITE_FG <= PL_FG_IDLE;
 			DONE <= '0';
 			READY <= '0';
-		elsif rising_edge(CLK) then
+		elsif falling_edge(CLK) then
 			case CLK_IDX is
 				when 0 =>
 					DONE <= '0';
@@ -60,6 +61,8 @@ begin
 			if CLK_IDX = PPU_PCEG_TOTAL_STAGES then
 				CLK_IDX := 0;
 			end if;
+
+			CLK_IDX_T <= CLK_IDX;
 		end if;
 	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 1a91b5e..cc9c24b 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -62,13 +62,14 @@ architecture Behavioral of ppu_sprite_bg is
 	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
 	signal T_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- output color buffer/register
+	signal BAM_ADDR_EN, TMM_ADDR_EN : boolean := false;
 begin
 	-- output drivers
 	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
-	BAM_ADDR <= R_BAM_ADDR when PL_STAGE = PL_BG_BAM_ADDR else (others => 'Z');
-	TMM_ADDR <= R_TMM_ADDR when PL_STAGE = PL_BG_TMM_ADDR else (others => 'Z');
 	T_BAM_DATA <= BAM_DATA;
 	T_TMM_DATA <= TMM_DATA;
+	BAM_ADDR <= R_BAM_ADDR when BAM_ADDR_EN else (others => 'Z');
+	TMM_ADDR <= R_TMM_ADDR when TMM_ADDR_EN else (others => 'Z');
 	-- CIDX combination
 	T_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
 
@@ -115,6 +116,12 @@ begin
 			R_TMM_ADDR <= (others => '0');
 			R_TMM_DATA <= (others => '0');
 		elsif rising_edge(CLK) then
+			BAM_ADDR_EN <= true when PL_STAGE = PL_BG_BAM_ADDR else false;
+			TMM_ADDR_EN <= true when PL_STAGE = PL_BG_TMM_ADDR else false;
+			-- R_BAM_ADDR <= T_BAM_ADDR;
+			-- R_BAM_DATA <= T_BAM_DATA;
+			-- R_TMM_ADDR <= T_TMM_ADDR;
+			-- R_TMM_DATA <= T_TMM_DATA;
 			case PL_STAGE is
 				when PL_BG_BAM_ADDR =>
 					R_BAM_ADDR <= T_BAM_ADDR;
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
index 2e48660..064d3ff 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_dispctl_pixclk/ppu_dispctl_pixclk.xci
@@ -88,7 +88,7 @@
         "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "6.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "90.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -173,7 +173,7 @@
         "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "MMCM_CLKOUT1_DIVIDE": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "90.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -339,7 +339,7 @@
         "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW1": [ { "value": "__npxclk__25.00000______0.000______50.0______191.696____114.212", "resolve_type": "generated", "usage": "all" } ],
-        "C_OUTCLK_SUM_ROW2": [ { "value": "__tpxclk___6.25000______0.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "__tpxclk___6.25000_____90.000______50.0______251.196____114.212", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
@@ -353,7 +353,7 @@
         "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -374,7 +374,7 @@
         "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -424,7 +424,7 @@
         "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "90.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],