merge `dev` into `ppu`

4 files changed, 143 insertions, 3 deletions

diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc
new file mode 100644
index 0000000..fa1dbd0
--- /dev/null
+++ b/basys3/basys3.srcs/io.xdc
@@ -0,0 +1,6 @@
+set_property PACKAGE_PIN A15 [get_ports SPI_CLK]
+set_property PACKAGE_PIN C15 [get_ports SPI_CS]
+set_property PACKAGE_PIN A17 [get_ports SPI_MOSI]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 638df89..0955506 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -144,8 +144,8 @@ architecture Behavioral of ppu is
 		
 		R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out
 	end component;
-	component ppu_dispctl port( -- display controller
-		CLK : in std_logic; -- system clock
+	component ppu_dispctl port(
+		SYSCLK : in std_logic; -- system clock
 		RESET : in std_logic;
 
 		X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x
@@ -299,7 +299,7 @@ begin
 		B => UB);
 
 	display_controller : component ppu_dispctl port map(
-		CLK => SYSCLK,
+		SYSCLK => SYSCLK,
 		RESET => SYSRST,
 		PREADY => PL_READY,
 		X => X,
diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd
new file mode 100644
index 0000000..cdf7d4a
--- /dev/null
+++ b/basys3/basys3.srcs/spi.vhd
@@ -0,0 +1,71 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use work.ppu_consts.all;
+
+entity spi is port (
+	SYSCLK : in std_logic; -- clock basys3 100MHz
+	SPI_CLK : in std_logic; -- incoming clock of SPI 
+	SPI_MOSI : in std_logic; -- incoming data of SPI
+	SPI_CS : in std_logic;   -- incoming select of SPI
+	DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); --  data read
+end spi;
+
+architecture Behavioral of spi is
+	signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0';	 -- signal for metastability synchronizer of clk SPI
+	signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0';		  -- signal for metastability synchronizer of data SPI
+	signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0';				  -- signal for metastability synchronizer of slave select SPI
+	
+	signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');	  -- signal to store incomming data of dataSPI (2x 8bit)
+	signal counter : integer := 23;									  -- counter for data position
+	signal enable : std_logic := '0';								   -- enable signal if slave is selected
+begin
+	
+	process (SYSCLK)
+	begin
+		if rising_edge(SYSCLK) then	   
+			-- flip flop for clk SPI to synchronise a
+			PulseFF0 <= SPI_CLK;
+			PulseFF1 <= PulseFF0;
+			PulseFF2 <= PulseFF1;
+			PulseFF3 <= PulseFF2;  
+			-- flip flop for data SPI to synchronise	  
+			dataFF0 <= SPI_MOSI;
+			dataFF1 <= dataFF0;
+			dataFF2 <= dataFF1;
+			dataFF3 <= dataFF2;			 
+			 -- flip flop for slave select SPI to synchronise				  
+			ssFF0 <= SPI_CS;
+			ssFF1 <= ssFF0;
+			ssFF2 <= ssFF1;
+			ssFF3 <= ssFF2; 
+			-- check if slave select signal has falling edge (slave is selected by master)	
+			if(ssFF3 = '1' and ssFF2 = '0') then
+			-- reset counter if true
+				counter <= 23;
+			-- disable data read if rising edge (slave is not selected)	
+			elsif (ssFF3 = '0' and ssFF2 = '1') then
+				enable <= '0';
+			end if;			
+			-- check if synchronised slave select signal is falling edge or data read is enabled
+			if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then
+				enable <= '1';										  -- enable data read
+				if (PulseFF3 = '0' and PulseFF2 = '1') then			 -- check for rising edge of clk SPI
+					if counter > -1 then								
+						counter <= counter - 1;
+						-- data transfer into vector  
+						SPI_REG(counter) <= dataFF3;
+					end if;
+				end if;
+				-- check if counter is done
+				if counter = -1 then
+					counter <= 23;	   -- reset counter 
+					DATA <= SPI_REG;			 
+				end if;	  
+			elsif (enable = '0') then
+				-- DATA <= SPI_REG;
+			end if;
+		end if;
+	end process;
+end Behavioral;
diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd
new file mode 100644
index 0000000..558489b
--- /dev/null
+++ b/basys3/basys3.srcs/top.vhd
@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity top is port (
+	SYSCLK : in std_logic; -- clock basys3 100MHz
+	RESET : in std_logic; -- global (async) system reset
+	SPI_CLK : in std_logic; -- incoming clock of SPI 
+	SPI_MOSI : in std_logic; -- incoming data of SPI
+	SPI_CS : in std_logic;   -- incoming select of SPI
+	WEN : in std_logic; -- PPU VRAM write enable
+	R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
+	NVSYNC, NHSYNC : out std_logic; -- native VGA out
+	TVBLANK, THBLANK : out std_logic); -- tiny VGA out
+end top;
+
+architecture Behavioral of top is
+	component ppu port(
+		CLK100 : in std_logic; -- system clock
+		RESET : in std_logic; -- global (async) system reset
+		EN : in std_logic; -- PPU VRAM enable (enable ADDR and DATA tri-state drivers)
+		WEN : in std_logic; -- PPU VRAM write enable
+		ADDR : in std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH-1 downto 0); -- PPU VRAM ADDR
+		DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
+		R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
+		NVSYNC, NHSYNC : out std_logic; -- native VGA out
+		TVBLANK, THBLANK : out std_logic); -- tiny VGA out
+	end component;
+	component spi port (
+		SYSCLK : in std_logic; -- clock basys3 100MHz
+		SPI_CLK : in std_logic; -- incoming clock of SPI 
+		SPI_MOSI : in std_logic; -- incoming data of SPI
+		SPI_CS : in std_logic;   -- incoming select of SPI
+		DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); --  data read
+	end component;
+
+	signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
+	alias SPI_DATA_ADDR is SPI_DATA(31 downto 16);
+	alias SPI_DATA_DATA is SPI_DATA(15 downto 0);
+begin
+	serial_peripheral_interface: component spi port map(
+		SYSCLK => SYSCLK,
+		SPI_CLK => SPI_CLK,
+		SPI_MOSI => SPI_MOSI,
+		SPI_CS => '1',
+		DATA => SPI_DATA);
+
+	picture_processing_unit: component ppu port map(
+		CLK100 => SYSCLK,
+		RESET => RESET,
+		EN => '1',
+		WEN => WEN,
+		ADDR => SPI_DATA_ADDR,
+		DATA => SPI_DATA_DATA,
+		R => R,
+		G => G,
+		B => B,
+		NVSYNC => NVSYNC,
+		NHSYNC => NHSYNC,
+		TVBLANK => TVBLANK,
+		THBLANK => THBLANK);
+end Behavioral;