ppu_dispctl test for valid VGA signal using DMT 640x480 @ 60

4 files changed, 89 insertions, 9 deletions

diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 846c7fb..8e9b494 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -52,15 +52,15 @@ package ppu_consts is
 	constant PPU_PL_TOTAL_STAGES : natural := 14;
 	-- VGA signal timings (https://tomverbeure.github.io/video_timings_calculator)
 	constant PPU_VGA_H_ACTIVE : natural := PPU_NATIVE_SCREEN_WIDTH;
-	constant PPU_VGA_H_PORCH_FRONT : natural := 16;
-	constant PPU_VGA_H_SYNC : natural := 64;
-	constant PPU_VGA_H_PORCH_BACK : natural := 80;
+	constant PPU_VGA_H_PORCH_FRONT : natural := 8;
+	constant PPU_VGA_H_SYNC : natural := 96;
+	constant PPU_VGA_H_PORCH_BACK : natural := 40;
 	constant PPU_VGA_H_BLANK : natural := PPU_VGA_H_PORCH_FRONT + PPU_VGA_H_SYNC + PPU_VGA_H_PORCH_BACK;
 	constant PPU_VGA_H_TOTAL : natural := PPU_VGA_H_BLANK + PPU_VGA_H_ACTIVE;
 	constant PPU_VGA_V_ACTIVE : natural := PPU_NATIVE_SCREEN_HEIGHT;
-	constant PPU_VGA_V_PORCH_FRONT : natural := 4;
-	constant PPU_VGA_V_SYNC : natural := 4;
-	constant PPU_VGA_V_PORCH_BACK : natural := 12;
+	constant PPU_VGA_V_PORCH_FRONT : natural := 2;
+	constant PPU_VGA_V_SYNC : natural := 2;
+	constant PPU_VGA_V_PORCH_BACK : natural := 25;
 	constant PPU_VGA_V_BLANK : natural := PPU_VGA_V_PORCH_FRONT + PPU_VGA_V_SYNC + PPU_VGA_V_PORCH_BACK;
 	constant PPU_VGA_V_TOTAL : natural := PPU_VGA_V_BLANK + PPU_VGA_V_ACTIVE;
 	constant PPU_VGA_SIGNAL_PIXEL_IDX_MAX : natural := PPU_VGA_V_TOTAL * PPU_VGA_H_TOTAL; -- horizontal and vertical pixel clock index
diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
index 725a6f2..a70a2e7 100644
--- a/basys3/basys3.srcs/ppu_dispctl.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -82,9 +82,9 @@ begin
 	U_POS_Y <= resize(N_POS_Y / 2, U_POS_Y'length);
 
 	ADDR_O <= std_logic_vector(resize(U_POS_X, ADDR_I'length)) when U_POS_Y(0) = '0' else std_logic_vector(resize(U_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH);
-	RO <= DATA_O(11 downto 8);
-	GO <= DATA_O(7 downto 4);
-	BO <= DATA_O(3 downto 0);
+	RO <= DATA_O(11 downto 8) when NACTIVE = '1' else (others => '0');
+	GO <= DATA_O(7 downto 4) when NACTIVE = '1' else (others => '0');
+	BO <= DATA_O(3 downto 0) when NACTIVE = '1' else (others => '0');
 
 	scanline_buffer : component ppu_dispctl_slbuf port map(
 		clka => CLK,
diff --git a/basys3/basys3.srcs/ppu_dispctl_demo.xdc b/basys3/basys3.srcs/ppu_dispctl_demo.xdc
new file mode 100644
index 0000000..44f2300
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_dispctl_demo.xdc
@@ -0,0 +1,35 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK100]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports HSYNC]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports VSYNC]
+set_property PACKAGE_PIN W5 [get_ports CLK100]
+set_property PACKAGE_PIN P19 [get_ports HSYNC]
+set_property PACKAGE_PIN R19 [get_ports VSYNC]
+
+
+set_property PACKAGE_PIN J18 [get_ports {B[3]}]
+set_property PACKAGE_PIN K18 [get_ports {B[2]}]
+set_property PACKAGE_PIN L18 [get_ports {B[1]}]
+set_property PACKAGE_PIN N18 [get_ports {B[0]}]
+set_property PACKAGE_PIN D17 [get_ports {G[3]}]
+set_property PACKAGE_PIN G17 [get_ports {G[2]}]
+set_property PACKAGE_PIN H17 [get_ports {G[1]}]
+set_property PACKAGE_PIN J17 [get_ports {G[0]}]
+set_property PACKAGE_PIN N19 [get_ports {R[3]}]
+set_property PACKAGE_PIN J19 [get_ports {R[2]}]
+set_property PACKAGE_PIN H19 [get_ports {R[1]}]
+set_property PACKAGE_PIN G19 [get_ports {R[0]}]
+
+set_property PACKAGE_PIN T18 [get_ports RESET]
+set_property IOSTANDARD LVCMOS33 [get_ports RESET]
diff --git a/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd b/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd
new file mode 100644
index 0000000..c4fa6b8
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_dispctl_demo_top.vhd
@@ -0,0 +1,45 @@
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use work.ppu_consts.all;
+
+entity ppu_dispctl_demo is port(
+	CLK100 : in std_logic; -- system clock
+	RESET : in std_logic; -- global (async) system reset
+	R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
+	VSYNC, HSYNC : out std_logic); -- vblank for synchronization
+end ppu_dispctl_demo;
+
+architecture Behavioral of ppu_dispctl_demo is
+	component ppu_dispctl port( -- display controller
+		CLK : in std_logic; -- system clock
+		RESET : in std_logic;
+
+		X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- tiny screen pixel x
+		Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- tiny screen pixel y
+		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- color in
+		PREADY : in std_logic; -- current pixel ready (pixel color is stable)
+
+		RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
+		NVSYNC, NHSYNC : out std_logic; -- VGA sync out
+		THBLANK, TVBLANK : out std_logic); -- tiny sync signals
+	end component;
+begin
+	display_controller : component ppu_dispctl port map(
+		CLK => CLK100,
+		RESET => RESET,
+		PREADY => '1',
+		X => open,
+		Y => open,
+		RI => (others => '1'),
+		GI => (others => '0'),
+		BI => (others => '1'),
+		RO => R,
+		GO => G,
+		BO => B,
+		NVSYNC => VSYNC,
+		NHSYNC => HSYNC,
+		TVBLANK => open,
+		THBLANK => open);
+end Behavioral;