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authorlonkaars <loek@pipeframe.xyz>2023-03-03 12:29:47 +0100
committerlonkaars <loek@pipeframe.xyz>2023-03-03 12:29:47 +0100
commit97990bc21cdd391b06dda72c0cf2f2e93b6867dc (patch)
tree1f6baac99db6dc337837f59a5a2e539058ea984a /basys3/basys3.srcs
parent9d998d2deb5fb1f90fd34ca10e4b44fc2bc8337d (diff)
fix apu_note_to_frequencyapu
Diffstat (limited to 'basys3/basys3.srcs')
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency.vhd5
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency_tb.vhd6
2 files changed, 6 insertions, 5 deletions
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 48defa3..17c396c 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -1,5 +1,6 @@
library ieee;
use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
@@ -13,7 +14,7 @@ entity apu_note_to_frequency is port (
end entity;
architecture Behavioral of apu_note_to_frequency is
- signal buff : std_logic_vector(15 downto 0) := (others => '0');
+ signal buff : std_logic_vector(11 downto 0) := (others => '0');
signal shift : integer;
begin
@@ -34,6 +35,6 @@ begin
x"100" when data(6 downto 3) = (x"C") else -- B 256
x"000";
- freq <= std_logic_vector( shift_right(unsigned(buff), natural(shift)) ); -- TODO: MAYBE WORKY???
+ freq <= std_logic_vector(shift_right(unsigned(buff), shift)); -- TODO: MAYBE WORKY???
end architecture;
diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
index f48a40c..d7a611a 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
@@ -10,11 +10,11 @@ end entity;
architecture Behavioral of apu_note_to_frequency_tb is
component apu_note_to_frequency is port(
- data : in std_logic_vector(7 downto 0);
+ data : in std_logic_vector(6 downto 0);
freq : out std_logic_vector(11 downto 0)); -- frequency
end component;
- signal data : std_logic_vector(7 downto 0) := (others => '0');
+ signal data : std_logic_vector(6 downto 0) := (others => '0');
signal freq : std_logic_vector(11 downto 0) := (others => '0');
signal ok : boolean := false;
@@ -26,7 +26,7 @@ begin
tb : process
begin
for i in 0 to 255 loop
- data <= std_logic_vector(to_unsigned(i, 8));
+ data <= std_logic_vector(to_unsigned(i, 7));
wait for 4 ps;
end loop;
end process;