new spi system

1 files changed, 13 insertions, 9 deletions

diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd
index ed1c3b0..1c58b60 100644
--- a/basys3/basys3.srcs/top.vhd
+++ b/basys3/basys3.srcs/top.vhd
@@ -8,7 +8,7 @@ entity top is port (
 	RESET : in std_logic; -- global (async) system reset
 	SPI_CLK : in std_logic; -- incoming clock of SPI 
 	SPI_MOSI : in std_logic; -- incoming data of SPI
-	WEN : in std_logic; -- PPU VRAM write enable
+	SPI_RESET : in std_logic; -- PPU VRAM write enable
 	DBG_DISP_ADDR : in std_logic; -- display address/data switch (debug)
 	DBG_LEDS_OUT : out std_logic_vector(15 downto 0); -- debug address/data output leds
 	R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
@@ -29,29 +29,33 @@ architecture Behavioral of top is
 	end component;
 	component spi port (
 		SYSCLK : in std_logic; -- clock basys3 100MHz
-		SPI_CLK : in std_logic; -- incoming clock of SPI 
-		SPI_MOSI : in std_logic; -- incoming data of SPI
 		RESET : in std_logic; -- async reset
-		DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); --  data read
+		DCK : in std_logic; -- data clock (spi format)
+		DI : in std_logic; -- data in (spi format)
+		DO : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); --	data out (parallel)
+		WEN : out std_logic); -- write enable (triggers during each word to propagate previous word)
 	end component;
 
+	signal SPI_RST, PPU_WEN : std_logic;
 	signal SPI_DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
 	alias SPI_DATA_ADDR is SPI_DATA(31 downto 16);
 	alias SPI_DATA_DATA is SPI_DATA(15 downto 0);
 begin
+	SPI_RST <= RESET or SPI_RESET;
 	serial_peripheral_interface: component spi port map(
 		SYSCLK => SYSCLK,
-		RESET => RESET,
-		SPI_CLK => SPI_CLK,
-		SPI_MOSI => SPI_MOSI,
-		DATA => SPI_DATA);
+		RESET => SPI_RST,
+		DCK => SPI_CLK,
+		DI => SPI_MOSI,
+		DO => SPI_DATA,
+		WEN => PPU_WEN);
 
 	DBG_LEDS_OUT <= SPI_DATA_ADDR when DBG_DISP_ADDR = '1' else SPI_DATA_DATA;
 
 	picture_processing_unit: component ppu port map(
 		CLK100 => SYSCLK,
 		RESET => RESET,
-		WEN => WEN,
+		WEN => PPU_WEN,
 		ADDR => SPI_DATA_ADDR,
 		DATA => SPI_DATA_DATA,
 		R => R,