diff options
| author | lonkaars <loek@pipeframe.xyz> | 2023-03-30 15:10:17 +0200 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2023-03-30 15:10:17 +0200 |
| commit | 6292c1101121bc8ba2db752cab3cbe41469b29d0 (patch) | |
| tree | b8cc9ac68b2c972b67d8aa4c9da84ea8c415a759 /basys3/basys3.srcs/spi_tb.vhd | |
| parent | 54b6ca70a74b3beb1331fd0b0bed28c665ed1f4d (diff) | |
new spi system
Diffstat (limited to 'basys3/basys3.srcs/spi_tb.vhd')
| -rw-r--r-- | basys3/basys3.srcs/spi_tb.vhd | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd index f6e2d21..8e4b8aa 100644 --- a/basys3/basys3.srcs/spi_tb.vhd +++ b/basys3/basys3.srcs/spi_tb.vhd @@ -12,18 +12,18 @@ end spi_tb; architecture behavioral of spi_tb is signal SYSCLK : std_logic := '0'; signal SPI_CLK : std_logic := '0'; - signal SPI_MOSI : std_logic := '0'; + signal SPI_DATA : std_logic := '0'; signal RESET : std_logic := '0'; - signal DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); begin uut : entity work.spi port map( SYSCLK => SYSCLK, RESET => RESET, - DATA => DATA, - SPI_CLK => SPI_CLK, - SPI_MOSI => SPI_MOSI); + DO => open, + DI => SPI_DATA, + DCK => SPI_CLK, + WEN => open); - sysclkgen: process + process begin for i in 0 to 10000 loop wait for 5 ns; @@ -34,197 +34,197 @@ begin wait; -- stop for simulator end process; - spi_data: process + process begin for i in 0 to 2 loop -- data = 0b01010110010100001001110011111111 (0x56509cff) - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '0'; + SPI_DATA <= '0'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; SPI_CLK <= '0'; - SPI_MOSI <= '1'; + SPI_DATA <= '1'; wait for 50 ns; SPI_CLK <= '1'; wait for 50 ns; |