debugged the ppu (still WIP, but some output is visible)

1 files changed, 11 insertions, 13 deletions

diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd
index 1560b54..a09d5df 100644
--- a/basys3/basys3.srcs/spi.vhd
+++ b/basys3/basys3.srcs/spi.vhd
@@ -16,15 +16,15 @@ architecture Behavioral of spi is
 	signal clkFF0,clkFF1,clkFF2,clkFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI
 	signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI
 
-	signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal counter : integer := 31; -- counter for data position
-
 	constant COUNTER_RESET_VALUE : integer := PPU_RAM_BUS_ADDR_WIDTH + PPU_RAM_BUS_DATA_WIDTH - 1;
 begin
 	process (SYSCLK)
+		variable bit_idx : integer range 0 to COUNTER_RESET_VALUE := COUNTER_RESET_VALUE; -- counter for data position
+		variable spi_reg : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0');
 	begin
 		if RESET = '1' then
-			 counter <= COUNTER_RESET_VALUE;
+			 spi_reg := (others => '0');
+			 bit_idx := COUNTER_RESET_VALUE;
 			 DATA <= (others => '0');
 		elsif rising_edge(SYSCLK) then
 			-- flip flop for clk SPI to synchronise a
@@ -39,17 +39,15 @@ begin
 			dataFF3 <= dataFF2;
 
 			if (clkFF3 = '0' and clkFF2 = '1') then -- check for rising edge of clk SPI
-				if counter > -1 then
-					counter <= counter - 1;
-					-- data transfer into vector
-					SPI_REG(counter) <= dataFF3;
+				spi_reg(bit_idx) := dataFF3; -- load new data into temporary register
+
+				if bit_idx = 0 then
+					bit_idx := COUNTER_RESET_VALUE; -- reset bit index
+					DATA <= spi_reg; -- flush temporary register to data outpu
+				else
+					bit_idx := bit_idx - 1; -- decrement bit index
 				end if;
 			end if;
-			-- check if counter is done
-			if counter = -1 then
-				counter <= COUNTER_RESET_VALUE; -- reset counter
-				DATA <= SPI_REG;
-			end if;
 		end if;
 	end process;
 end Behavioral;