update style guide and format code

1 files changed, 63 insertions, 93 deletions

diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd
index f47df48..0e496f6 100644
--- a/basys3/basys3.srcs/ppu_vga_tiny.vhd
+++ b/basys3/basys3.srcs/ppu_vga_tiny.vhd
@@ -1,103 +1,73 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 22.02.2023 13:13:03
--- Design Name: 
--- Module Name: ppu_vga_tiny - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
 
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ppu_vga_tiny is
-  Port ( 
-  		CLK: in std_logic; -- system clock
-		RESET: in std_logic;
+entity ppu_vga_tiny is port (
+	CLK : in std_logic; -- system clock
+	RESET : in std_logic;
 
-		X: out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y: out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		
-		VSYNC, VBLANK, 
-		HSYNC, HBLANK: out std_logic); -- VGA sync outputs 
+	X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+	Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 
+	VSYNC, VBLANK,
+	HSYNC, HBLANK : out std_logic); -- VGA sync outputs
 end ppu_vga_tiny;
 
 architecture Behavioral of ppu_vga_tiny is
-  signal hcount: STD_LOGIC_VECTOR(PPU_POS_H_WIDTH-1 downto 0):= (others => '0');
-  signal vcount: STD_LOGIC_VECTOR(PPU_POS_V_WIDTH-1 downto 0):= (others => '0');
-  signal CLKcounter: STD_LOGIC_VECTOR(4 downto 0):= (others => '0');
-  
+	signal hcount : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal vcount : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
+	signal clk_counter : std_logic_vector(4 downto 0) := (others => '0');
 begin
-process (CLK) 
-begin
-    if rising_edge(CLK) then
-        CLKcounter <= CLKcounter + 1;
-        if(CLKcounter > 15) then
-            clkCounter <= (others => '0');
-            -- x,y data uit
-            X <= hcount;
-            Y <= vcount;
-             
-            --pulse width
-            if hcount < 32 or hcount >= 320-80 then
-                hsync <= '0';
-            else
-                hsync <= '1';
-            end if;
-        
-            if vcount < 8 or vcount >= 240-15 then
-                vsync <= '0';
-            else
-                vsync <= '1';
-            end if;
-             
-            -- Hblank and Vblank outputs
-            if hcount >= 320-80 then
-                hblank <= '1';
-            else
-                hblank <= '0';
-            end if;
-            
-            if vcount >= 240-15 then
-                vblank <= '1';
-            else
-                vblank <= '0';
-            end if;
-             
-            -- sync pulse time
-            hcount <= hcount + 1;
-             
-            if hcount = 400 then
-                vcount <= vcount + 1;
-                hcount <= (others => '0');
-            end if;
-            
-            if vcount = 255 then	   
-                vcount <= (others => '0');
-            end if;
-        end if;
-    end if;
-end process;
+	process (CLK)
+	begin
+		if rising_edge(CLK) then
+			clk_counter <= clk_counter + 1;
+			if(clk_counter > 15) then
+				clk_counter <= (others => '0');
+				-- x,y data out
+				X <= hcount;
+				Y <= vcount;
+
+				--pulse width
+				if hcount < 32 or hcount >= 320-80 then
+					hsync <= '0';
+				else
+					hsync <= '1';
+				end if;
+
+				if vcount < 8 or vcount >= 240-15 then
+					vsync <= '0';
+				else
+					vsync <= '1';
+				end if;
+
+				-- Hblank and Vblank outputs
+				if hcount >= 320-80 then
+					hblank <= '1';
+				else
+					hblank <= '0';
+				end if;
+
+				if vcount >= 240-15 then
+					vblank <= '1';
+				else
+					vblank <= '0';
+				end if;
+
+				-- sync pulse time
+				hcount <= hcount + 1;
+
+				if hcount = 400 then
+					vcount <= vcount + 1;
+					hcount <= (others => '0');
+				end if;
 
+				if vcount = 255 then
+					vcount <= (others => '0');
+				end if;
+			end if;
+		end if;
+	end process;
 end Behavioral;