diff options
author | lonkaars <loek@pipeframe.xyz> | 2023-02-20 11:23:30 +0100 |
---|---|---|
committer | lonkaars <loek@pipeframe.xyz> | 2023-02-20 11:23:30 +0100 |
commit | d2eb1cf5055a19f3e276ce737428b06332de63b3 (patch) | |
tree | f70c6fc4e29660efa5c4c6ad02c1730c08f0fd19 /basys3/basys3.srcs/ppu_pceg_tb.vhdl | |
parent | 9b84c25a53b7269228743e398b13c19af505226b (diff) |
rename .vhdl to .vhd
Diffstat (limited to 'basys3/basys3.srcs/ppu_pceg_tb.vhdl')
-rw-r--r-- | basys3/basys3.srcs/ppu_pceg_tb.vhdl | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhdl b/basys3/basys3.srcs/ppu_pceg_tb.vhdl deleted file mode 100644 index 137d4b4..0000000 --- a/basys3/basys3.srcs/ppu_pceg_tb.vhdl +++ /dev/null @@ -1,47 +0,0 @@ -library ieee; -library unisim; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use unisim.vcomponents.all; - -entity ppu_pceg_tb is -end ppu_pceg_tb; - -architecture behavioral of ppu_pceg_tb is - component ppu_pceg port( - CLK: in std_logic; -- system clock - RESET: in std_logic; -- async reset - SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch - COMP_PAL: out std_logic; -- compositor + palette lookup - DONE: out std_logic); -- last pipeline stage done - end component; - signal CLK: std_logic := '0'; - signal RESET: std_logic := '0'; - signal SPRITE: std_logic; - signal COMP_PAL: std_logic; - signal DONE: std_logic; - -begin - uut: ppu_pceg port map( - CLK => CLK, - RESET => RESET, - SPRITE => SPRITE, - COMP_PAL => COMP_PAL, - DONE => DONE); - - tb: process - begin - for i in 0 to 32 loop - if i > 20 then - RESET <= '1'; - end if; - - wait for 5 ns; - CLK <= '1'; - wait for 5 ns; - CLK <= '0'; - end loop; - wait; -- stop for simulator - end process; -end; |