update code style

1 files changed, 12 insertions, 12 deletions

diff --git a/basys3/basys3.srcs/ppu_pceg_tb.vhd b/basys3/basys3.srcs/ppu_pceg_tb.vhd
index 137d4b4..719ec06 100644
--- a/basys3/basys3.srcs/ppu_pceg_tb.vhd
+++ b/basys3/basys3.srcs/ppu_pceg_tb.vhd
@@ -10,27 +10,27 @@ end ppu_pceg_tb;
 
 architecture behavioral of ppu_pceg_tb is
 	component ppu_pceg port(
-		CLK: in std_logic; -- system clock
-		RESET: in std_logic; -- async reset
-		SPRITE: out std_logic; -- sprite info fetch + sprite pixel fetch
-		COMP_PAL: out std_logic; -- compositor + palette lookup
-		DONE: out std_logic); -- last pipeline stage done
+		CLK : in std_logic; -- system clock
+		RESET : in std_logic; -- async reset
+		SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch
+		COMP_PAL : out std_logic; -- compositor + palette lookup
+		DONE : out std_logic); -- last pipeline stage done
 	end component;
-	signal CLK: std_logic := '0';
-	signal RESET: std_logic := '0';
-	signal SPRITE: std_logic;
-	signal COMP_PAL: std_logic;
-	signal DONE: std_logic;
+	signal CLK : std_logic := '0';
+	signal RESET : std_logic := '0';
+	signal SPRITE : std_logic;
+	signal COMP_PAL : std_logic;
+	signal DONE : std_logic;
 
 begin
-	uut: ppu_pceg port map(
+	uut : ppu_pceg port map(
 		CLK => CLK,
 		RESET => RESET,
 		SPRITE => SPRITE,
 		COMP_PAL => COMP_PAL,
 		DONE => DONE);
 
-	tb: process
+	tb : process
 	begin
 		for i in 0 to 32 loop
 			if i > 20 then