WIP fg sprite optimilization

1 files changed, 8 insertions, 10 deletions

diff --git a/basys3/basys3.srcs/ppu_pceg.vhd b/basys3/basys3.srcs/ppu_pceg.vhd
index 1aaeee4..5d9f4d6 100644
--- a/basys3/basys3.srcs/ppu_pceg.vhd
+++ b/basys3/basys3.srcs/ppu_pceg.vhd
@@ -1,25 +1,23 @@
 library ieee;
 use ieee.std_logic_1164.all;
---use ieee.numeric_std.all;
+use work.ppu_consts.all;
 
 entity ppu_pceg is port(
 	CLK : in std_logic; -- system clock
 	RESET : in std_logic; -- async reset
 	SPRITE : out std_logic; -- sprite info fetch + sprite pixel fetch
-	COMP_PAL : out std_logic; -- compositor + palette lookup
-	DONE : out std_logic); -- last pipeline stage done
+	DONE : out std_logic; -- last pipeline stage done
+	READY : out std_logic); -- rgb buffer propagation ready
 end ppu_pceg;
 
 architecture Behavioral of ppu_pceg is
-	constant PPU_PL_TOTAL_STAGES : natural := 14;
-
-	type states is (PL_SPRITE, PL_COMP_PAL, PL_DONE);
+	type states is (PL_SPRITE, PL_DONE, PL_READY);
 	signal state : states := PL_SPRITE;
 begin
 	-- output drivers
 	SPRITE <= CLK when RESET = '0' and state = PL_SPRITE else '0';
-	COMP_PAL <= CLK when RESET = '0' and state = PL_COMP_PAL else '0';
-	DONE <= '1' when RESET = '0' and state = PL_DONE else '0';
+	DONE <= CLK when RESET = '0' and state = PL_DONE else '0';
+	READY <= '1' when RESET = '0' and state = PL_READY else '0';
 
 	process(CLK, RESET)
 		variable CLK_IDX : natural range 0 to PPU_PL_TOTAL_STAGES+1 := 0;
@@ -31,9 +29,9 @@ begin
 			if CLK_IDX < 4 then
 				state <= PL_SPRITE;
 			elsif CLK_IDX < 5 then
-				state <= PL_COMP_PAL;
-			else
 				state <= PL_DONE;
+			else
+				state <= PL_READY;
 			end if;
 
 			-- increment clock counter