diff options
| author | lonkaars <loek@pipeframe.xyz> | 2023-03-12 19:46:49 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2023-03-12 19:46:49 +0100 |
| commit | b247b52429f2fc6aecd29539ec5afa0d47218147 (patch) | |
| tree | 7b17a37202f595f6c7c718fd30846200fc606e19 /basys3/basys3.srcs/ppu_dispctl_tb.vhd | |
| parent | 57da22cb15825b975d9fac499138413550903b25 (diff) | |
upscaler test with coe initialized rom
Diffstat (limited to 'basys3/basys3.srcs/ppu_dispctl_tb.vhd')
| -rw-r--r-- | basys3/basys3.srcs/ppu_dispctl_tb.vhd | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/basys3/basys3.srcs/ppu_dispctl_tb.vhd b/basys3/basys3.srcs/ppu_dispctl_tb.vhd index deb3d48..e54a304 100644 --- a/basys3/basys3.srcs/ppu_dispctl_tb.vhd +++ b/basys3/basys3.srcs/ppu_dispctl_tb.vhd @@ -14,8 +14,6 @@ architecture behavioral of ppu_dispctl_tb is signal RESET : std_logic := '0'; signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0'); signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0'); - signal RI,GI,BI : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); - signal PREADY : std_logic := '0'; signal RO,GO,BO : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); signal NVSYNC, NHSYNC : std_logic := '0'; signal THBLANK, TVBLANK : std_logic := '0'; @@ -23,12 +21,12 @@ begin uut : entity work.ppu_dispctl port map( SYSCLK => SYSCLK, RESET => RESET, - PREADY => PREADY, + PREADY => '1', X => X, Y => Y, - RI => RI, - GI => GI, - BI => BI, + RI => (others => '1'), + GI => (others => '0'), + BI => (others => '1'), RO => RO, GO => GO, BO => BO, @@ -40,9 +38,9 @@ begin process begin for i in 0 to 3200000 loop - wait for 5 ps; + wait for 5 ns; SYSCLK <= '1'; - wait for 5 ps; + wait for 5 ns; SYSCLK <= '0'; end loop; wait; -- stop for simulator |